Figure 36 8 Lane 1G Iod Cdr Design In Polarfire - Microchip Technology Microsemi PolarFire Demo Manual

Appendix: Multi-Lane 1G IOD CDR Design
To conclude, the following IOD resources are used to create an 8-lane design in a PolarFire MPF300
device:
• One PF_IOD_CDR_CCC with a lane controller for DLL delay update
• 8 I/O Lanes and lane controllers for clock recovery
•
The following figure shows the high-level block diagram of an 8-lane design implemented using Libero
SoC PolarFire.
Figure 36 • 8 Lane 1G IOD CDR Design in PolarFire
Board
RJ45
RJ45
RJ45
RJ45
RJ45
RJ45
RJ45
RJ45
As shown in Figure 36,
2 to form eight links. The clock conditioning circuit (CCC) available in the South-West corner, is
configured in the PLL-DLL cascaded mode for the clock recovery and DLL delay update.
Apart from 8 lane controllers for clock recovery, an additional lane controller from the
PF_IOD_CDR_CCC is inferred during synthesis for sharing the DLL delay update. This optimizes the
utilization of lane controllers in the device.
REF_CLK
PHY
PF_IOD_CDR_CCC
(SW Corner)
RX
TX
LINK 1
TX_CLK_G_TO_CDR
RX
TX
LINK 2
RX
TX
LINK 3
RX
TX
LINK 4
RX
TX
LINK 5
RX
TX
LINK 6
RX
TX
LINK 7
RX
TX
LINK 8
page 32, eight PF_IOD_CDR instances are instantiated from GPIO Banks 5 and
Microsemi Proprietary DG0799 Demo Guide Revision 3.0
FPGA
GPIO BANK 5
0°
PF_IOD_CDR_0
90°
180°
RX_CLK_R
270°
DLL_DELAY_CODE
PF_IOD_CDR_1
DLL_DELAY_CODE
RX_CLK_R
TX_CLK_G
PF_IOD_CDR_2
DLL_DELAY_CODE
RX_CLK_R
TX_CLK_G
PF_IOD_CDR_3
DLL_DELAY_CODE
RX_CLK_R
TX_CLK_G
PF_IOD_CDR_4
DLL_DELAY_CODE
RX_CLK_R
TX_CLK_G
PF_IOD_CDR_5
DLL_DELAY_CODE
RX_CLK_R
TX_CLK_G
GPIO BANK 2
PF_IOD_CDR_6
DLL_DELAY_CODE
RX_CLK_R
TX_CLK_G
PF_IOD_CDR_7
DLL_DELAY_CODE
RX_CLK_R
TX_CLK_G
32