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Related Manuals for Microchip Technology Microsemi PolarFire
Summary of Contents for Microchip Technology Microsemi PolarFire
- Page 1 DG0799 Demo Guide PolarFire FPGA 1G Ethernet loopback Using IO CDR...
- Page 2 About Microsemi ©2019 Microsemi, a wholly owned Microsemi, a wholly owned subsidiary of Microchip Technology Inc. (Nasdaq: MCHP), offers a comprehensive portfolio of subsidiary of Microchip Technology Inc. All semiconductor and system solutions for aerospace & defense, communications, data center and industrial markets.
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Page 3: Table Of Contents
Contents 1 Revision History ........... . . 1 Revision 3.0 . - Page 4 Figures Figure 1 Block Diagram ..............4 Figure 2 Top-Level Libero Implementation .
- Page 5 Tables Table 1 Design Requirements ............2 Table 2 I/O Signals .
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Page 6: Revision History
Revision History Revision History The revision history describes the changes that were implemented in the document. The changes are listed by revision, starting with the most current publication. Revision 3.0 The following is a summary of changes made in this revision. •... -
Page 7: Polarfire Fpga 1G Ethernet Loopback Using Iod Cdr
PolarFire FPGA 1G Ethernet Loopback Using IOD CDR ® Microsemi PolarFire FPGAs support 1G (1000BASE-T) Ethernet solutions for various networking applications. In PolarFire devices, 10/100/1000 Mbps (1G) Ethernet is implemented using the CoreTSE media access control (MAC) soft IP core. The CoreTSE IP implements a serial gigabit media- independent interface (SGMII) with an Ethernet PHY. -
Page 8: Prerequisites
PolarFire FPGA 1G Ethernet Loopback Using IOD CDR Table 1 • Design Requirements (continued) Requirement Version Libero SoC Design Suite v12.1 Prerequisites Before you start: Download the reference design files from: http://soc.microsemi.com/download/rsc/?f=mpf_dg0799_eval_liberosocv12p1_df Download and install Libero SoC v12.1 on the host PC from https://www.microsemi.com/product-directory/design-resources/1750-libero-soc#downloads The latest versions of ModelSim and Synplify Pro are included in the Libero SoC PolarFire installation package. -
Page 9: About Pf_Iod_Cdr
PolarFire FPGA 1G Ethernet Loopback Using IOD CDR Figure 1 • Block Diagram PolarFire Evaluation Board MDIO Interface PolarFire FPGA RX_P RX DATA SGMII RX_N Host PC RX_DATA PF_IOD_CDR Ethernet Test VSC8575 RJ45 CoreTSE Solution Ethernet 1250 Mbps (cat KARAT, Copper Wireshark) TX_DATA... -
Page 10: Design Implementation
PolarFire FPGA 1G Ethernet Loopback Using IOD CDR 2.3.2 Design Implementation Figure 2, page 5 shows the top-level Libero implementation of the demo design. Figure 2 • Top-Level Libero Implementation Table 2, page 5 lists the important I/O signals of the design. Table 2 •... -
Page 11: Ip Configuration
PolarFire FPGA 1G Ethernet Loopback Using IOD CDR Table 2 • I/O Signals (continued) Signal Direction Description REF_CLK_SEL Output Reference clock speed pin of the VSC PHY. Held high for selecting the 125 MHz reference clock speed. RD_BC_ERROR Output CoreTSE receive error signal. This LED signal indicates the receive code group error. -
Page 12: Figure 4 Coretse_0 Configurator
PolarFire FPGA 1G Ethernet Loopback Using IOD CDR Figure 4 • CORETSE_0 Configurator 2.3.3.3 pf_init_monitor_0 The pf_init_monitor_0 (PF_INIT_MONITOR) block is used to issue a reset signal to the user logic (FABRIC_RESET_N). To ensure a glitch-free reset, the DEVICE_INIT_DONE signal is connected to the CORERESET_PF IP with a lock signal from the PF_CCC macro. -
Page 13: Figure 5 Mi-V Configurator
PolarFire FPGA 1G Ethernet Loopback Using IOD CDR 2.3.3.6 Mi-V Soft Processor The Mi-V soft processor supports RISC-V processor-based designs. The Mi-V soft processor executes the application from the LSRAM mapped at 0x80000000. It configures the ZL30364 clock generation hardware through the CoreSPI IP and the VSC PHY through the CoreTSE MDIO interface. It also configures the CoreTSE registers using the AHB interface. -
Page 14: Figure 7 Pf_Ccc_0 Input Clock Configuration
PolarFire FPGA 1G Ethernet Loopback Using IOD CDR Figure 7 • PF_CCC_0 Input Clock Configuration Microsemi Proprietary DG0799 Demo Guide Revision 3.0... -
Page 15: Figure 8 Pf_Ccc_0 Output Clock Configuration
PolarFire FPGA 1G Ethernet Loopback Using IOD CDR Figure 8, page 10 shows the PF_CCC_0 output clock configuration. This design uses an 80-MHz system clock for configuring the APB peripherals. Figure 8 • PF_CCC_0 Output Clock Configuration 2.3.3.9 PF_IOD_CDR_CCC_C0 The PF_IOD_CDR_CCC IP used for generating high-speed bank clocks for PF_IOD_CDR. This IP is in PLL-DLL cascaded mode to generate high-speed bank clocks of four phases 0, 90, 180, 270 from a 125 MHz input. -
Page 16: Figure 10 Corespi_0 Configurator
PolarFire FPGA 1G Ethernet Loopback Using IOD CDR 2.3.3.10 CORESPI_0 The CORESPI_0 (CoreSPI) block is a controller IP, which implements SPI communication. Mi-V configures the ZL30364 clock generation hardware using the CORESPI_0 block. The following points describe the CoreSPI_0 configuration, as shown in Figure 10, page 11. -
Page 17: Figure 11 Mi-V Processor Bus Interface Memory Map
PolarFire FPGA 1G Ethernet Loopback Using IOD CDR 2.3.3.12 Design Memory Map Figure 11, page 12 shows the Mi-V processor bus interface memory map. Figure 11 • Mi-V Processor Bus Interface Memory Map 2.3.3.13 CoreAHBLite_0 CoreAHBLite_0 is configured as shown in Figure 12, page 13 to interface the PF_SRAM for accessing the LSRAM at memory address 0x8000_0000. -
Page 18: Figure 12 Coreahblite_0 Configuration
PolarFire FPGA 1G Ethernet Loopback Using IOD CDR Figure 12 • CoreAHBLite_0 Configuration 2.3.3.14 CoreAHBLite_2 CoreAHBLite_2 is configured as shown in Figure 13, page 14 to interface the APB peripherals to the Mi- V processor at 0x6000_0000. Microsemi Proprietary DG0799 Demo Guide Revision 3.0... -
Page 19: Figure 13 Coreahblite_2 Configuration
PolarFire FPGA 1G Ethernet Loopback Using IOD CDR Figure 13 • CoreAHBLite_2 Configuration 2.3.3.15 CoreAPB3 CoreAPB3 is configured as shown in Figure 14, page 15 to connect the peripherals CoreTSE, CoreSPI, and CoreUARTapb as slaves. • APB Master Data bus width: 32 bit •... -
Page 20: Figure 14 Coreapb3 Configuration
PolarFire FPGA 1G Ethernet Loopback Using IOD CDR Figure 14 • CoreAPB3 Configuration 2.3.3.16 COREAHBTOAPB3_0 The COREAHBTOAPB3 IP is used to bridge between AHB and APB3. This IP retains the default configuration. Microsemi Proprietary DG0799 Demo Guide Revision 3.0... -
Page 21: Clocking Structure
PolarFire FPGA 1G Ethernet Loopback Using IOD CDR Clocking Structure In the demo design, there are two clock sources—the on-board 50 MHz oscillator and the on-board ZL30364 clock generation hardware. • On-board 50 MHz oscillator: This oscillator drives the PLL that generates an 80-MHz clock for the Mi-V soft processor and peripherals. -
Page 22: Libero Design Flow
Libero Design Flow Libero Design Flow This chapter describes the Libero design flow for running this demo design, which includes: • Synthesize, page 18 • Place and Route, page 18 • Verify Timing, page 18 • Generate FPGA Array Data, page 19 •... -
Page 23: Synthesize
Libero Design Flow Synthesize To synthesize the design: On the Design Flow tab, double-click Synthesize. When the synthesis is successful, a green tick mark appears next to Synthesize, as shown in Figure 16, page 17. Right-click Synthesize and select View Report to view the synthesis report and log files in the Reports tab. -
Page 24: Generate Fpga Array Data
Libero Design Flow On the Design Flow tab, double-click Verify Timing. When the design successfully meets the timing requirements, a green tick mark appears next to Ver- ify Timing, as shown in Figure 16, page 17. Right-click Verify Timing and select View Report to view the verify timing report and log files in the Reports tab. -
Page 25: Configure Design Initialization Data And Memories
Libero Design Flow Configure Design Initialization Data and Memories The fabric RAM blocks must be initialized with the user application to configure the PHY and management registers of CoreTSE. The user application (HEX file) is generated using SoftConsole. This step is used to select the fabric RAM client (HEX file), its storage location (sNVM/µPROM/SPI Flash), and generate the fabric RAM client. -
Page 26: Generate Bitstream
Libero Design Flow Figure 19 • Fabric RAM Tab Apply Option On the Design Flow tab, double-click Generate Design Initialization Data. When the LSRAM initialization client is successfully generated in sNVM, a green tick mark appears next to Generate Design Initialization Data, as shown in Figure 16, page 17. -
Page 27: Figure 20 Board Setup
Libero Design Flow Connect the RJ45 cable from the host PC to the J15 connector (RJ45-PORT 0) on the board. This is required for the Ethernet link after programming. The following figure shows the board setup for programming the device. Figure 20 •... -
Page 28: Programming The Device Using Flashpro Express
Programming the Device Using FlashPro Express Programming the Device Using FlashPro Express This chapter describes how to program the PolarFire device with the job file using Flashpro Express. The job file is available at the following design files folder location: mpf_dg0799_eval_liberosocv12p1_df\Programming_Job Follow these steps: Connect the jumpers and set up the PolarFire Evaluation Kit Board as described in steps 1 to 5 of... -
Page 29: Figure 23 Programming The Device
Programming the Device Using FlashPro Express The FlashPro Express window appears as shown in Figure 23, page 24. Confirm that a programmer number appears in the Programmer field. If it does not, confirm the board connections and click Refresh/Rescan Programmers. Figure 23 •... -
Page 30: Running The Demo
Running the Demo Running the Demo This section describes how to run the 1G loopback demo. The procedure involves transmitting packets from the network card of the host PC to the board using Cat Karat and verifying the packets transmitted to and received from the board using Wireshark. -
Page 31: Figure 26 Host Pc Ethernet Network Connection
Running the Demo From the control panel of the host PC, note the name of Ethernet Network connection, as shown in Figure 26, page 26. On a Windows 10 machine, this connection is Ethernet. Figure 26 • Host PC Ethernet Network Connection In the Cat Karat Packet Builder window >... -
Page 32: Figure 28 Packet Flow And View Settings
Running the Demo In Packet Flow pane, select the use RAW check box, and set Packets per Burst to 5 and the Data Pattern to 55, as shown in Figure 28, page 27. Figure 28 • Packet Flow and View Settings Open the Wireshark software from the Start menu of the host PC. -
Page 33: Figure 30 Wireshark Interface Settings
Running the Demo Double-click Local Area Connection and select the interface settings, as shown in Figure 30, page 28. On a Window 10 machine, select Ethernet. Figure 30 • Wireshark Interface Settings 10. Click the Start a new live capture icon, as shown in Figure 31, page 28. -
Page 34: Figure 32 Wireshark Live Capture
Running the Demo The Wireshark live capture displays the Ethernet packets transferred from the board to the host PC network card, as shown in Figure 32, page 29. Figure 32 • Wireshark Live Capture 11. In the Cat Karat window, click Start Transmit to transmit five packets from the host PC to the board, as shown in Figure 33, page 29. -
Page 35: Figure 34 Transmitted And Looped Back Packets
Running the Demo 12. Verify that 10 packets have been captured (transmitted and received), as shown in Figure 34, page 30. Figure 34 • Transmitted and Looped Back Packets The preceding figure highlights five packets that were transmitted from the host PC to the board, looped back at the CoreTSE IP, and sent back to the host PC. -
Page 36: Appendix: Multi-Lane 1G Iod Cdr Design
Appendix: Multi-Lane 1G IOD CDR Design Appendix: Multi-Lane 1G IOD CDR Design In a multi-lane design, Ethernet traffic from multiple RJ45 cables, comes into the FPGA via PHY. In such cases, multiple RX and TX ports must be assigned from the PolarFire GPIO Banks to form multiple SGMII links with the PHY. -
Page 37: Figure 36 8 Lane 1G Iod Cdr Design In Polarfire
Appendix: Multi-Lane 1G IOD CDR Design To conclude, the following IOD resources are used to create an 8-lane design in a PolarFire MPF300 device: • One PF_IOD_CDR_CCC with a lane controller for DLL delay update • 8 I/O Lanes and lane controllers for clock recovery •... -
Page 38: Appendix: 1G Ethernet Base-T And Base-X Using Transceiver
Appendix: 1G Ethernet BASE-T and BASE-X Using Transceiver Appendix: 1G Ethernet BASE-T and BASE-X Using Transceiver The PolarFire FPGA family includes multiple embedded low-power, performance-optimized transceivers. Each transceiver has both the physical medium attachment (PMA), protocol physical coding sub-layer (PCS) logic, and interfaces to the FPGA fabric. The transceiver has a multi-lane architecture with each lane natively supporting serial data transmission rates from 250 Mbps to 12.7 Gbps. -
Page 39: Transceiver Configuration
Appendix: 1G Ethernet BASE-T and BASE-X Using Transceiver The following points summarize the 1G Ethernet BASE-T and BASE-X designs: • The Mi-V soft processor is used to configure the PHY registers (using MDIO interface), MAC Configuration and Management registers. User can also implement a fabric logic or any other soft processor to implement these functions. -
Page 40: Transceiver Connections
Appendix: 1G Ethernet BASE-T and BASE-X Using Transceiver Table 6 • XCVR Configuration (continued) Parameters Settings CDR reference clock frequency 125 MHz PCS-fabric interface width 10 bits FPGA interface frequency 125 MHz PMA Mode Enabled Clocks and Resets TX clock Regional RX clock Regional... -
Page 41: Table 5 Table
Appendix: 1G Ethernet BASE-T and BASE-X Using Transceiver Table 7 • XCVR Port Connections (continued) Port Name Input or Output Connection Description CLKS_FROM_TX_PLL XCVR transmit clock sourced from the TX PLL. LANE0_RXD_N Differential receive input pads for LANE0_RXD_P receiving the Ethernet data. LANE0_CDR_REF_CLK 125 MHz reference for clock and data recovery. -
Page 42: Appendix: References
Appendix: References Appendix: References This section lists documents that provide more information about and about the IP cores used in the 1G loopback demo design and about PolarFire 1G Ethernet Solutions in general. • For more information about PF_IOD_CDR_CCC and PF_IOD_CDR, see UG0686: PolarFire FPGA User I/O User Guide.
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