Minimizing Power Consumption (Pdiss); Power Dissipation Variation With Junction Temperature - ST STM32 Application Note

4.2

Minimizing power consumption (Pdiss)

To reduce the power consumption, the first action is to reduce the supply voltage. Some STM32 devices offer a
multi-power domain architecture that allows the different power domains to be set in low-power mode to optimize
the power efficiency (see the product datasheets for more details).
The power consumption profile varies also with the application. Some applications are most of the time in Idle
mode, working on full or limited capacity only when an event occurs. Some others demand a regular workload.
For these various power profiles, the user programmer enables the low power modes, in the software, and then
allows power saving.
The most common available modes are listed below:
• Power gating: reduces power consumption by shutting off the current to block of the circuit that are not in
use.
• Clock gating: reduces dynamic power dissipation by shutting down clocks to a circuit or portion of clock
tree.
• Dynamic voltage scaling: power management technique where the voltage is increased or decreased,
depending upon circumstances.
• Dynamic frequency scaling (also known as CPU throttling): frequency automatically adjusted on-the-fly
depending on the actual needs, to conserve power and reduce the amount of heat generated.
All these modes are available for example on STM32H7 Series and STM32MP1 Series products (see related
reference manuals for more details).
4.3

Power dissipation variation with junction temperature

In this section, process, voltage and activity factors are kept constant and there is a focus on the effect of junction
temperature.
The static/leakage current grows exponentially with the junction temperature (whilst the dynamic current does not
significantly change).
The power dissipation variation with junction temperature has the following main consequences:
• A cooling solution must be implemented to limit the junction temperature below 125 °C (maximum junction
temperature).
• If the cooling system is not efficient enough, the device can go in thermal runaway that may be destructive.
When performing system-level thermal simulations in the design phase, it is fundamental to input junction
temperature dependent power dissipation.
AN5036 - Rev 3
AN5036
Minimizing power consumption (Pdiss)
page 8/28