Digital Input Channel; Digital Output And Dac Channels; Fig. 3-1. Illustration Of The Personnel Principle For Acquiring Adc Data - L-Card ADC Series User Manual

Номер
Logical
логического
ADC
канала АЦП
number
Канал 1
Channel 1
Канал 2
Channel 2
Канал 3
Channel 3

Fig. 3-1. Illustration of the personnel principle for acquiring ADC data

3.3.3. Digital input channel.

Synchronous digital input occurs with a period of t
where n ={1,2,...,2097152} is a configurable frequency division factor for synchronous
din
digital input.

3.3.4. Digital output and DAC channels

Synchronous digital output, as well as updating both channels of the DAC, occurs with a period
of 2* t . If the data buffer for the output and the DAC is empty, then the last value is held at the
ref
outputs.
With any DAC channel and digital output, you can work asynchronously, with the other
channels assigned as synchronous, the same synchronous mode is supported: either a streaming or an
self-oscillator from an internal buffer.
3.3.4.1. Restrictions on the current implementation of asynchronous output during
external synchronization.
Asynchronous output to digital lines and to DAC in the operating mode will always work when
configured for internal synchronization. But asynchronous output to digital lines and to the DAC will
not function in the standby mode for external synchronization of the start of data acquisition or
waiting for more than 1 μs of the external clock of the ADC conversion.
Кадр
Frame
t
k
n =3
k
1 2 3
t
sw
Момент сэмплирования отсчётов данных АЦП
Sampling timing of ADC data
Interframe
Межкадровая
задержка
delay
t
d
1
t
ch
* n ,
ref din
Interframe
Межкадровая
Кадр
Frame
задержка
t
k
2 3
delay