Fig. 3-2. Synchronization System Structure In E-502 - L-Card ADC Series User Manual

Генератор
Generator
2.0 / 1,5 МГц
DI_SYN1
Внешняя
External
синхронизация
DI_SYN2
synchronization
CONV_IN
От ведущего
From the master
START_IN
E-502
E-502
X1...X16
Y1...Y16
GND32
f
ref
Синхр.
Synch.
3.3.5.2. Secondary synchronization.
The functionality of the secondary synchronization is embedded in the project,
!
but is not currently implemented. You can find out about the availability of this
functionality
The secondary synchronization circuit (II) is the ADC data selection circuit depending on
the secondary synchronization conditions, operating exclusively against the background of the
previously started clock signal from the output of the primary synchronization circuit (I), i.e. against
the background of the started data stream of the ADC.
The following ADC data resolution synchronization modes are supported:
•
No synchronization (transparency mode)
•
Synchronization from an analog signal in the selected ADC channel
•
Digital synchronization with the selected signal from the inputs DI1 ... DI16, or
DI_SYN1, or DI_SYN2
The following modes of sensitivity to the fluctuations of the synchronization signal are
supported:
•
Enable of ADC data on the edge (drop) of an analog or digital signal
•
Enable of ADC data at a level "above the threshold" or "below the threshold" (for analog
synchronization) or at the logic level "1" (for digital synchronization)
The following ADC data inhibit modes are supported:
•
Software prohibition (stop) with the possibility of re-authorization (if the previously set
enable condition is repeated) without restarting the primary synchronization scheme
Общие условия синхронизации всех процессов ввода-вывода
General synchronization conditions for all I/O processes
в E-502 (выбор опорной частоты и условий старта)
in E-502 (selection of reference frequency and start conditions)
I
MHz
Схема
Primary
первичной
synchroniz
синхрони-
f
ation
ref
зации
scheme
E-502
E-502
Синхр.
Synch.
Комму-
Вход
Input
Switch
татор
Схема селекции
Scheme of ADC
данных АЦП в
data selection in
Управля
Control
зависимости
dependence
ющая
table
от вторичных
from the
таблица
условий
secondary
синхронизации
synchronization
conditions
DI_SYN1
DI_SYN2

Fig. 3-2. Synchronization system structure in E-502

in the sales department of
CONV_OUT
START_OUT
DI_SYN1
Узел
DI_SYN2
Digital
цифр.
input
DI1...DI16
ввода
node
Узел
Выход
Output
ADC
АЦП
node
I I
Cхема вторичной
ADC secondary
синхронизации
synchronization
данных АЦП
data scheme
Поток данных "на ввод"
Data flow "to input"
L-Card.
К ведомому
To E-502
E-502
slave
Синхр.
Synch.
Синхр.
Synch.
Узел
DAC and
ЦАП и
digital
цифрового
output node
вывода
Поток данных "на вывод"
Data flow "to output"
DAC1
DAC2
DO1...DO16