Relative Delays Of The Adc, Dac And I/O Channels; Fig.3-4. Synchronous I/O Diagram - L-Card ADC Series User Manual

3.3.8. Relative delays of the ADC, DAC and I/O channels.

t
t
ST_SU
W
CONV_OUT
START_OUT
X,Y,
GND32
t
ADC_SU
Выборка
Sample
Внутренний
Internal 1-го отсчёта АЦП
1st ADC count
преобразо-
t
converter
ADC
ватель (АЦП)
(ADC)
Выборка
Sample
1-го отсчёта DI
1st DI count
t
t
DI_SU DI_H
DI
DO
DAC1,
DAC2
In the above-mentioned synchronous I/O diagram, the output signal CONV_OUT is used as a
reference clock signal, with respect to which all I/O delays are described. Temporal parameters of the
diagram are described in the table below. The delays in the ADC channel are given for the operating
mode without averaging the data and without allocating additional cycles of the ADC for setting the
signal
Description
Reference frequency period
Duration of the signal pulse CONV_OUT
Group delay time of analog channel of ADC
channel in E-502
The delay time from the front CONV_OUT
to the sampling time of the ADC chip
The time to set the state "1" to
START_OUT before the front
CONV_OUT
(start of data collection)
t
REF
Выборка
Sample
2-го отсчёта АЦП
2nd ADC count
Выборка
Sample
2-го отсчёта DI
2nd DI count
2*t
REF
1-ый отсчёт DO
1st DO count
1-ый отсчёт DAC1, DAC2
1st DAC1, DAC2 count

Fig.3-4. Synchronous I/O diagram

Выборка
Sample
3-го отсчёта АЦП
3rd ADC count
Выборка
Sample
3-го отсчёта DI
3rd DI count
2*t
REF
t
DO
2-ый отсчёт DO
2nd DO count
t
DAC
2-ый отсчёт DAC1, DAC2
2nd DAC1, DAC2 count
Desig-
nation
Minimum
t
REF
t
W
t
ADC_SU
t
ADC
t 45 ns
ST_SU
t
ST_H
3-ий отсчёт DO
3rd DO count
Timing sample
Typical Maximum
500 ns (2 MHz)
667 ns (1.5 MHz)
50 ns
15-70 ns
0 ns
3-ий отсчёт
3rd DAC1,
DAC1, DAC2 DAC2 count