Operation Principle - L-Card ADC Series User Manual

configuration is possible: 8-bit 2-directional data bus + up to 8 data bits per input + up to 8 data bits
per output. This allows the implementation of controlling bus diagrams for complex digital
4.4.2.2
devices (sec. , p.
With synchronous output to the DAC to digital output, operation only in the same
!
synchronous mode is supported: in the mode of streaming output, or a self-oscillator from
the internal buffer. At the same time, you can work asynchronously with any output
channels.
Note the limitations of the asynchronous output for external synchronization (n.
Digital input, up to 17 lines, synchronous mode of up to 2 MHz or asynchronous one. In
synchronous mode, the stream from digital lines is synchronous with the ADC stream, but separate
and independent of the settings of the ADC data collection frame (the frequency of data collection by
digital lines is set separately and does not depend on the ADC frame settings).
It should be noted that in the E-502, the three highest digits in the group of digital inputs (DI14,
DI15, DI16) have alternative synchronization functions (
The ADC, DAC, digital input and output streams are synchronized with respect to the same f
reference frequency, which can be assigned programmatically: 1.5 MHz or 2 MHz.
Hardware-wise, in E-502, the physical frequency of the ADC and the synchronous digital input
is always equal to f
ref
Getting all the fractional frequences of the data input f
(where m and n are natural numbers) occurs at the hardware processing level in the FPGA and/or in
the Blackfin processor.
E-502 has a mechanism of the intermodule synchronization (s.
synchronous I/O system.
E-502 has a 32-bit data word format, in the format of which, besides the actual data for input
or output, there is also a physical channel number. This hardware binding of the physical channel
number ensures that the channel number is mistaken even if the top-level program for some reason
lost an arbitrary amount of data.
For advanced users: HOST DMA access mode to the internal memory of the signal processor
ADSP-BF523 allows you to apply an independent access channel to the Blackfin internal memory.
This creates a huge convenience - "transparency" with low-level Blackfin programming - to see what
happens in Blackfin memory on an independent channel. To some extent, HOST DMA can replace
JTAG (the convenience of the technology of independent access channel in the signal processor
memory has been evaluated by users even in products E-440/ E14-440 by L-CARD!).
Operation modes with E-502 via USB or Ethernet are alternative. E-502 uses 32 bit data words
for a transmission via interfaces (in each word the data is counted with the index part).
When using USB, the E-502 has a bandwidth limitation of 5 Mcounts/ s High-Speed, which
must be taken into account while applying the E-502.
When operating via Ethernet, the E-502 has a 2.5 Mcounts/s bandwidth limit on the input.
The interface function (USB, Ethernet) in E-502 is performed by a separate 2 cores ARM
controller LPC4333/4337, which has a separate JTAG connector on the board and an independent
additional UART0 port.

3.3. Operation principle

In section 3.2the general information about E-502 was summarized, in this section further
details are presented. This section in many respects repeats a similar section of the manual L-502 due
to the similarity of these projects.
38
).
, and the physical refresh rate of each DAC channel and digital output is f
table 4-2
).
/n and f /2m output fractional frequencies
ref ref
3.3.5
, p.
3.3.4.1
).
ref
20
) to form a single
ref
/2.