Digital Input Channel; Digital Output And Dac Channels; Fig. 3-1. Illustration Of The Personnel Principle For Acquiring Adc Data - L-Card L-502-P-G-D-I User Manual

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can be 2.0 or 1.5 MHz for an internal synchronization or ≤2.0 MHz for an external,
where f
ref
n = {1,2,..., 256}, n
к
The above-mentioned frame structure of the ADC data is shown in
example, a 3-channel ADC mode operation (n
ADC logical
Номер
логического
channel
канала АЦП
number
Канал 1
Channel 1
Канал 2
Channel 2
Канал 3
Channel 3

Fig. 3-1. Illustration of the personnel principle for acquiring ADC data

3.3.3. Digital input channel.

Synchronous digital input occurs with a period of t
where n
={1,2,...,2097152} is a configurable frequency division factor for synchronous
din
digital input

3.3.4. Digital output and DAC channels

Synchronous digital output, as well as updating both channels of the DAC, occurs with a
period of 2* t . If the data buffer for the output and the DAC is empty, then the last value is held at
ref
the outputs.
={1,2,...,2097152}, n
sw
Кадр
Frame
t
k
n =3
k
1 2
t
sw
Момент сэмплирования отсчётов данных АЦП
Sampling time of ADC samples
={0,1,...,2097151}.
d
к = 3) is taken with a non-zero interframe delay t
Межкадровая
Interframe
задержка
delay
t
d
3 1
t
ch
* n ,
ref din
3.3: Operation principle
fig. 3-1
. Here, for
Interframe
Межкадровая
Кадр
Frame
задержка
t
k
2 3
.
d
delay