Epson S5U1C17001C Manual page 295

Instruction List (9)
Mnemonic
Classification
Opcode
jreq / jreq.d sign7
Branch
sjreq / sjreq.d label±imm20
sign20
xjreq / xjreq.d label±imm24
sign24
jrne / jrne.d sign7
sjrne / sjrne.d label±imm20
sign20
xjrne / xjrne.d label±imm24
sign24
call / call.d %rb
sign10
scall / scall.d label±imm20
sign20
xcall / xcall.d label±imm24
sign24
calla / calla.d %rb
imm7
scalla / scalla.d label±imm20
imm20
xcalla / xcalla.d label±imm24
imm24
ret / ret.d
int imm5
intl imm5, imm3
reti / reti.d
brk
retd
Shift and swap sr %rd, %rs
%rd, imm7
sa %rd, %rs
%rd, imm7
sl %rd, %rs
%rd, imm7
swap %rd, %rs
∗1)
Remarks
Number of bits to be shifted: Zero to three bits when rs/imm7 = 0–3, four bits when rs/imm7 = 4–7, eight bits when rs/imm7 ≥ 8
Operand
pc←pc+2+sign8 if Z is true; sign8={sign7,0}
pc←label±imm20 if Z is true
pc←pc+2+sign20 if Z is true
pc←label±imm24 if Z is true
pc←pc+2+sign24 if Z is true
pc←pc+2+sign8 if !Z is true; sign8={sign7,0}
pc←label±imm20 if !Z is true
pc←pc+2+sign20 if !Z is true
pc←label±imm24 if !Z is true
pc←pc+2+sign24 if !Z is true
sp←sp-4, A[sp]←pc+2(d=0)/4(d=1), pc←pc+2+rb
sp←sp-4, A[sp]←pc+2(d=0)/4(d=1), pc←pc+2+sign11; sign11={sign10,0}
sp←sp-4, A[sp]←pc+2(d=0)/4(d=1), pc←label±imm20
sp←sp-4, A[sp]←pc+2(d=0)/4(d=1), pc←pc+2+sign20
sp←sp-4, A[sp]←pc+2(d=0)/4(d=1), pc←label±imm24
sp←sp-4, A[sp]←pc+2(d=0)/4(d=1), pc←pc+2+sign24
sp←sp-4, A[sp]←pc+2(d=0)/4(d=1), pc←rb
sp←sp-4, A[sp]←pc+2(d=0)/4(d=1), pc←imm7
sp←sp-4, A[sp]←pc+2(d=0)/4(d=1), pc←label±imm20
sp←sp-4, A[sp]←pc+2(d=0)/4(d=1), pc←imm20
sp←sp-4, A[sp]←pc+2(d=0)/4(d=1), pc←label±imm24
sp←sp-4, A[sp]←pc+2(d=0)/4(d=1), pc←imm24
pc←A[sp](23:0), sp←sp+4
sp←sp-4, A[sp]←{psr, pc+2}, pc←vector (TTBR+imm5×4)
sp←sp-4, A[sp]←{psr, pc+2}, pc←vector (TTBR+imm5×4), psr(IL)←imm3
{psr, pc}←A[sp], sp←sp+4
A[DBRAM]←{psr, pc+2}, A[DBRAM+4]←r0, pc←0xfffc00
r0←A[DBRAM+4](23:0), {psr, pc}←A[DBRAM]
Logical shift to right: rd(15:0)←rd(15:0)>>rs(15:0), rd(23:16)←0, zero enters to MSB (∗1)
Logical shift to right: rd(15:0)←rd(15:0)>>imm7, rd(23:16)←0, zero enters to MSB (∗1)
Arithmetical shift to right: rd(15:0)←rd(15:0)>>rs(15:0), rd(23:16)←0, sign copied to MSB (∗1)
Arithmetical shift to right: rd(15:0)←rd(15:0)>>imm7, rd(23:16)←0, sign copied to MSB (∗1)
Logical shift to left: rd(15:0)←rd(15:0)<<rs(15:0), rd(23:16)←0, zero enters to LSB (∗1)
Logical shift to left: rd(15:0)←rd(15:0)<<imm7, rd(23:16)←0, zero enters to LSB (∗1)
rd(15:8)←rs(7:0), rd(7:0)←rs(15:8), rd(23:16)←0
Function
Assembly Programming
Flags
D
IL IE C V Z N
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