Epson S5U1C17001C Manual page 273

CMOS 16-bit Single Chip Microcomputer
S1C17 Family C Compiler Package
Quick Reference
for Development
Registers (S1C17 Core)
General-purpose Registers (8)
23
R7
R6
R5
R4
R3
R2
R1
R0
Memory Map and Trap Table (S1C17 Core)
Memory Map
0xff ffff
0xff fc00
0xff fbff
0x00 0000
Special Registers (3)
0
23
PC
23
SP
7
Reserved Core I/O area
1K bytes
Internal memory/
Internal peripherals/
User area
0
Program counter
0
Stack pointer
0
PSR
Processor status register
Trap Table
No.
0 (0x00) Reset
1 (0x01) Address misaligned interrupt
2 (0x02) NMI
3 (0x03) Maskable external interrupt 3
: :
31 (0x1f) Maskable external interrupt 31
(Can be read from address 0xffff80.)
PSR
7 6 5 4
IL[2:0] IE
Initial value 0 0 0 0
IL[2:0]: Interrupt level (0–7: Enabled interrupt level)
IE: Interrupt enable (1: Enabled, 0: Disabled)
Z: Zero flag (1: Zero, 0: Non zero)
N: Negative flag (1: Negative, 0: Positive)
C: Carry flag (1: Carry/borrow, 0: No carry)
V: Overflow flag (1: Overflow, 0: Not overflown)
S1C17 Core
Vector
address
TTBR + 0x00
TTBR + 0x04
TTBR + 0x08
TTBR + 0x0c
:
TTBR + 0x7c
TTBR: Trap table start address
S1C17 Core
3 2 1 0
C V Z N
0 0 0 0