Intel Stratix 10 Mx Hbm2 Controller Architecture - Intel Stratix 10 MX HBM2 IP User Manual

2 Intel Stratix 10 MX HBM2 Architecture
UG-20031 | December 2017
Figure 4. Intel Stratix 10 MX HBM2 Interface Using HBM2 Channels 0 and 7 through
the UIBSS
There is one AXI interface per Pseudo Channel. The AXI4 protocol can handle
concurrent writes and reads to the HBM2 controller. There is also a sideband user port
per user channel pair, compliant to the Advanced Peripheral Bus (APB). The sideband
provides access to user-controlled features such as refresh requests.
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Intel Stratix 10 MX HBM2 Controller Details

2.3 Intel Stratix 10 MX HBM2 Controller Architecture

The hardened HBM2 controller provides a controller per Pseudo Channel.
Each controller consists of a write and read data path and the control logic that helps
to translate user commands to the HBM2 memory. The control logic accounts for the
HBM2 memory specification timing and schedules commands in an efficient manner.
The following figure shows a block diagram of the HBM2 controller, corresponding to
channel 0. Each channel consists of two AXI ports (one per Pseudo Channel), and a
sideband APB interface, which lets you issue requests, such as auto-refresh, to the
HBM2.
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Intel Stratix 10 MX HBM2 IP User Guide
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