Table Of Contents - Intel Stratix 10 MX HBM2 IP User Manual

Contents
1 Introduction to High Bandwidth Memory......................................................................... 3
1.1 HBM2 in Intel Stratix 10 MX Devices......................................................................... 3
1.2 HBM2 DRAM Structure.............................................................................................4
1.3 Intel Stratix 10 MX HBM2 Features............................................................................4
1.4 Intel Stratix 10 MX HBM2 Controller Features............................................................. 5
2 Intel Stratix 10 MX HBM2 Architecture............................................................................ 6
2.1 Intel Stratix 10 MX HBM2 Introduction.......................................................................6
2.2 Intel Stratix 10 MX HBM2 Architecture.......................................................................6
2.3 Intel Stratix 10 MX HBM2 Controller Architecture........................................................ 9
2.3.1 Intel Stratix 10 MX HBM2 Controller Details.................................................. 10
3 Generating the Intel Stratix 10 MX HBM2 IP.................................................................. 14
3.1 Parameterizing the Intel Stratix 10 MX HBM2 IP........................................................ 15
3.2 General Parameters for Intel Stratix 10 MX HBM2 IP.................................................. 15
3.3 Controller Parameters for Intel Stratix 10 MX HBM2 IP............................................... 17
3.4 Diagnostic Parameters for Intel Stratix 10 MX HBM2 IP.............................................. 19
3.5 Example Designs Parameters for Intel Stratix 10 MX HBM2 IP..................................... 21
3.6 Generating the Example Design.............................................................................. 22
3.7 Intel Stratix 10 MX HBM2 IP Example Design for Synthesis......................................... 23
4 Simulating the Intel Stratix 10 MX HBM2 IP.................................................................. 25
4.1 Intel Stratix 10 MX HBM2 IP Example Design............................................................ 25
4.2 Simulating Intel Stratix 10 MX HBM2 IP with ModelSim*............................................ 26
4.3 Simulating Intel Stratix 10 MX HBM2 IP with Synopsys VCS*...................................... 27
4.4 Simulating Intel Stratix 10 MX HBM2 IP with Riviera-PRO*......................................... 27
4.5 Simulating Intel Stratix 10 MX HBM2 IP for High Efficiency......................................... 27
5 Intel Stratix 10 MX HBM2 IP Interface........................................................................... 30
5.1 Intel Stratix 10 MX HBM2 IP High Level Block Diagram...............................................30
5.2 Intel Stratix 10 MX HBM2 IP Controller Interface Signals............................................ 30
5.2.1 Clock Signals............................................................................................30
5.2.2 Reset Signals........................................................................................... 31
5.2.3 AXI User-interface Signals..........................................................................32
5.3 User AXI Interface Timing...................................................................................... 36
5.3.1 AXI Write Transaction................................................................................ 37
5.3.2 AXI Read Transaction.................................................................................38
6 Intel Stratix 10 MX HBM2 IP Controller Performance..................................................... 40
6.1 Intel Stratix 10 MX HBM2 Bandwidth....................................................................... 40
6.2 Intel Stratix 10 MX HBM2 IP Efficiency..................................................................... 40
6.3 Intel Stratix 10 MX HBM2 IP Latency....................................................................... 42
6.4 Intel Stratix 10 MX HBM2 IP Timing.........................................................................42
7 Document Revision History for Intel Stratix 10 MX HBM2 IP User Guide........................43
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Intel Stratix 10 MX HBM2 IP User Guide
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Contents