Intel Stratix 10 MX HBM2 IP User Manual page 34

Port Name
axi_0_0_wuser_strb
axi_0_0_wlast
axi_0_0_wvalid
axi_0_0_wready
Table 17. User Port 0's Write Response Channel
Port Name
axi_0_0_bid
axi_0_0_bresp
axi_0_0_bvalid
axi_0_0_bready
Table 18. User Port 0's AXI4 Read Address (Command) Channel
Port Name
axi_0_0_arid
axi_0_0_araddr
axi_0_0_arlen
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Intel Stratix 10 MX HBM2 IP User Guide
34
Width Direction
2 Input
1 Input
1 Input
1 Output
Width Direction
9 Output
2 Output
1 Output
1 Input
Width Direction
9 Input
28/29 Input
8 Input
5 Intel Stratix 10 MX HBM2 IP Interface
UG-20031 | December 2017
Description
Extra Write Strobes (AXI WUSER port). Indicates
which byte lanes (for u0_wuser_data) hold valid
data, signal is aligned to u0_wstrb.
Write Last. Indicates the last transfer in a write
burst.
Write Valid. Indicates that valid write data and
strobes are available
Write Ready. Indicates that the slave (HBM2
controller) can accept write data.
Description
Response ID Tag. The ID tag of the write
response.
Write response. Indicates the status of the write
transaction.
• 2'b00 = OKAY; indicates that normal access
is successful.
Write response valid. Indicates that the channel
is signaling a valid write response.
Response ready. Indicates that the master can
accept a write response.
Desription
Read address ID. The ID tag for the read
address group of signals.
Read address. The address of the first transfer
in a read burst transaction. This address bus is
28-bits wide for a 4 GB device and 29-bits wide
for an 8 GB device. You must tie the lower-
order five bits to 0.
The system derives the address configuration of
the higher-order bits from the following
information; the order depends on the address
ordering that you choose:
• Bank Address(BA) – 4 bits wide. BA[3:2]
are used as Bank Group(BG) bits
• Row Address(RA) - 14 bits wide.
• Column Address (COL) - 6 bits wide. COL[0]
is tied to 0 for 32B access and COL[1:0] is
tied to 0 for 64B access.
• Stack ID (SID) – 1 bit wide, and applies
only to 8 GB/8H devices. The HBM2
controller uses the SID serves as a higher
order BA bit. The SID is not available in 4
GB devices.
Refer to the Address Ordering section for logical
address mapping details.
Burst Length. The burst length gives the exact
number of transfers in a burst. The HBMC
supports only one BL4 or BL8 transaction.
• 0b00000000 = Burst length of 1.
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