Intel Stratix 10 MX HBM2 IP User Manual page 7

2 Intel Stratix 10 MX HBM2 Architecture
UG-20031 | December 2017
Figure 3. Block Diagram of Intel Stratix 10 MX HBM2 Implementation
The user core clock drives the logic highlighted in green, while the UIB clocks the logic
highlighted in blue. The UIB clock also drives the HBM2 interface clock. User logic can
run up to one-to-four times slower than the HBM2 interface.
Soft Logic AXI Adaptor
The HBM2 IP also includes a soft logic adaptor implemented in core logic. The soft
logic adaptor gates the user valid signals (
, and
valid
from the HBM2 controller. The soft logic adapter also temporarily stores output from
the HBM2 controller (AXI write response and AXI read data channels) when the AXI
ready signal is absent. You can disable the temporary storage logic if user logic is
always ready to accept output from the HBM2 controller through the parameter editor
when generating the HBM2 IP.
HBM2 DRAM
The HBM2 DRAM is ideal for high-bandwidth operation to multiple DRAM devices
across many independent interfaces called channels. Each channel provides access to
an independent set of DRAM banks. Requests from one channel cannot access data
attached to another channel.
Each HBM2 channel consists of an independent command and data interface to and
from the HBM2 DRAM. A channel provides access to a discrete pool of memory in the
DRAM device; no channel can access the memory storage for another channel. Each
channel interface provides an independent interface to a specific number of banks of
DRAM of a defined page size.
The following table lists the HBM2 signals that interface to the UIB. The UIB drives the
HBM2 signals and decodes the received data from the HBM2. These signals cannot be
accessed through the AXI4 User Interface.
read address valid
write address valid
) with the corresponding pipelined ready signals
®
Intel Stratix
,
write data
®
10 MX HBM2 IP User Guide
7