Atmel AVR ATtiny15L Manual page 32

Timer/Counter1 Output
Compare RegisterB – OCR1B
ATtiny15L
32
Figure 22. Effects of Unsynchronized OCR Latching
Synchronized OC1A Latch
Unsynchronized OC1A Latch
During the time between the write and the latch operation, a read from OCR1A will read
the contents of the temporary location. This means that the most recently written value
always will read out of OCR1A.
When OCR1A contains $00 or the top value, as specified in OCR1B Register, the output
PB1(OC1A) is held low or high according to the settings of COM1A1/COM1A0. This is
shown in Table 13.
Bit 7 6
$2D MSB
Read/Write R/W R/W
Initial Value 1 1
The Output Compare Register1 (OCR1B) is an 8-bit read/write register. This register is
used in the PWM mode only, and it limits the top value to which the Timer/Counter1
keeps counting. After reaching OCR1B in PWM mode, the counter starts from $00.
Table 13. PWM Outputs when OCR1A = $00 or OCR1B
COM1A1
1
1
1
1
In PWM mode, the Timer Overflow Flag (TOV1) is set as in normal Timer/Counter
mode. Timer Overflow Interrupt1 operates exactly as in normal Timer/Counter mode,
i.e., it is executed when TOV1 is set provided that Timer Overflow Interrupt and global
interrupts are enabled. This also applies to the Timer Output Compare A Flag and
interrupt.
Compare Value Changes
Compare Value Changes
Glitch
5 4 3
R/W R/W R/W
1 1 1
COM1A0 OCR1B
0 $00
0 OCR1B
1 $00
1 OCR1B
Counter Value
Compare Value
PWM Output OC1A
Counter Value
Compare Value
PWM Output OC1A
2 1 0
LSB OCR1B
R/W R/W R/W
1 1 1
Output PWMn
L
H
H
L
1187H–AVR–09/07