Table of Contents
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Features
•
High Performance, Low Power 32-bit AVR
– Compact Single-Cycle RISC Instruction Set Including DSP Instructions
– Read-Modify-Write Instructions and Atomic Bit Manipulation
– Performance
• Up to 64 DMIPS Running at 50MHz from Flash (1 Flash Wait State)
• Up to 36 DMIPS Running at 25MHz from Flash (0 Flash Wait State)
– Memory Protection Unit (MPU)
• Secure Access Unit (SAU) providing user defined peripheral protection
®
•
picoPower
Technology for Ultra-Low Power Consumption
•
Multi-Hierarchy Bus System
– High-Performance Data Transfers on Separate Buses for Increased Performance
– 12 Peripheral DMA Channels Improve Speed for Peripheral Communication
•
Internal High-Speed Flash
– 64Kbytes, 32Kbytes, and 16Kbytes Versions
– Single-Cycle Access up to 25MHz
™
– FlashVault
Technology Allows Pre-programmed Secure Library Support for End
User Applications
– Prefetch Buffer Optimizing Instruction Execution at Maximum Speed
– 100,000 Write Cycles, 15-year Data Retention Capability
– Flash Security Locks and User Defined Configuration Area
•
Internal High-Speed SRAM, Single-Cycle Access at Full Speed
– 16Kbytes (64Kbytes and 32Kbytes Flash), or 8Kbytes (16Kbytes Flash)
•
Interrupt Controller (INTC)
– Autovectored Low Latency Interrupt Service with Programmable Priority
•
External Interrupt Controller (EIC)
•
Peripheral Event System for Direct Peripheral to Peripheral Communication
•
System Functions
– Power and Clock Manager
™
– SleepWalking
Power Saving Control
– Internal System RC Oscillator (RCSYS)
– 32 KHz Oscillator
– Multipurpose Oscillator and Digital Frequency Locked Loop (DFLL)
•
Windowed Watchdog Timer (WDT)
•
Asynchronous Timer (AST) with Real-Time Clock Capability
– Counter or Calendar Mode Supported
•
Frequency Meter (FREQM) for Accurate Measuring of Clock Frequency
•
Six 16-bit Timer/Counter (TC) Channels
– External Clock Inputs, PWM, Capture and Various Counting Capabilities
•
PWM Channels on All I/O Pins (PWMA)
– 8-bit PWM up to 150MHz Source Clock
•
Four Universal Synchronous/Asynchronous Receiver/Transmitters (USART)
– Independent Baudrate Generator, Support for SPI
– Support for Hardware Handshaking
•
One Master/Slave Serial Peripheral Interfaces (SPI) with Chip Select Signals
– Up to 15 SPI Slaves can be Addressed
•
Two Master and Two Slave Two-Wire Interfaces (TWI), 400kbit/s I
•
One 8-channel Analog-To-Digital Converter (ADC) with up to 12 Bits Resolution
– Internal Temperature Sensor
®
Microcontroller
2
C-compatible
®
32-bit AVR
Microcontroller
AT32UC3L064
AT32UC3L032
AT32UC3L016
Preliminary
Summary
32099DS–06/2010
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Table of Contents
Related Manuals for Atmel AT32UC3L064
Summary of Contents for Atmel AT32UC3L064
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Page 1: Features
Microcontroller – High-Performance Data Transfers on Separate Buses for Increased Performance – 12 Peripheral DMA Channels Improve Speed for Peripheral Communication • Internal High-Speed Flash AT32UC3L064 – 64Kbytes, 32Kbytes, and 16Kbytes Versions – Single-Cycle Access up to 25MHz AT32UC3L032 ™... - Page 2 AT32UC3L016/32/64 • Eight Analog Comparators (AC) with Optional Window Detection • Capacitive Touch (CAT) Module ® ® – Hardware Assisted QTouch and QMatrix Touch Acquisition ® ® – Supports QTouch and QMatrix Capture from Capacitive Touch Sensors ® • QTouch Library Support –...
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Page 3: Description
AT32UC3L016/32/64 1. Description The AT32UC3L is a complete System-On-Chip microcontroller based on the AVR32 UC RISC processor running at frequencies up to 50MHz. AVR32 UC is a high-performance 32-bit RISC microprocessor core, designed for cost-sensitive embedded applications, with particular empha- sis on low power consumption, high code density, and high performance. - Page 4 One touch sensor can be configured to operate autonomously without software interaction, allowing wakeup from sleep modes when activated. Atmel offers the QTouch library for embedding capacitive touch buttons, sliders, and wheels functionality into AVR microcontrollers. The patented charge-transfer signal acquisition offers robust sensing and included fully debounced reporting of touch keys and includes Adjacent Key ®...
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Page 5: Overview
AT32UC3L016/32/64 2. Overview Block Diagram Figure 2-1. Block Diagram MCKO MDO[5..0] LOCAL BUS LOCAL BUS MSEO[1..0] INTERFACE AVR32UC CPU EVTI_N NEXUS EVTO_N CLASS 2+ MEMORY PROTECTION UNIT JTAG 16/8 KB INTERFACE SRAM INSTR DATA INTERFACE INTERFACE DATAOUT aWire RESET_N 64/32/16 KB HIGH SPEED FLASH BUS MATRIX... -
Page 6: Configuration Summary
AT32UC3L016/32/64 Configuration Summary Table 2-1. Configuration Summary Feature AT32UC3L064 AT32UC3L032 AT32UC3L016 Flash 64KB 32KB 16KB SRAM 16KB 16KB GPIO High-drive pins External Interrupts USART Peripheral DMA Channels Peripheral Event System Asynchronous Timers Timer/Counter Channels PWM channels Frequency Meter Watchdog Timer... -
Page 7: Package And Pinout
AT32UC3L016/32/64 3. Package and Pinout Package The device pins are multiplexed with peripheral functions as described in Section 3.2. Figure 3-1. TQFP48/QFN48 Pinout PA15 PA21 PA16 PB10 PA17 RESET_N PA19 PB04 PA18 PB05 VDDIO VDDCORE PB11 VDDIN PB01 PA10 PA07 PA12 PA01 VDDIO... - Page 8 AT32UC3L016/32/64 Figure 3-2. TLLGA48 Pinout PA21 PA16 PB10 PA17 RESET_N PA19 PB04 PA18 PB05 VDDIO VDDCORE PB11 VDDIN PB01 PA10 PA07 PA12 PA01 VDDIO 32099DS–06/2010...
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Page 9: Peripheral Multiplexing On I/O Lines
AT32UC3L016/32/64 Peripheral Multiplexing on I/O lines 3.2.1 Multiplexed signals Each GPIO line can be assigned to one of the peripheral functions.The following table describes the peripheral signals multiplexed to the GPIO lines. Table 3-1. GPIO Controller Function Multiplexing GPIO Function Supply Type Normal... - Page 10 AT32UC3L016/32/64 Table 3-1. GPIO Controller Function Multiplexing Normal ADCIFB- PWMA- EIC- PA18 VDDIO TC0-B1 GLOC-IN[4] CAT-SYNC CAT-CSB[0] AD[4] PWMA[18] EXTINT[5] Normal ADCIFB- TWIMS1- PWMA- CAT- PA19 VDDIO TC0-A2 CAT-SYNC AD[5] TWALM PWMA[19] CSA[10] Normal USART2- PWMA- SCIF- CAT- PA20 VDDIN TC0-A1 GLOC-IN[3] PWMA[20]...
- Page 11 AT32UC3L016/32/64 3.2.2 Peripheral Functions Each GPIO line can be assigned to one of several peripheral functions. The following table describes how the various peripheral functions are selected. The last listed function has priority in case multiple functions are enabled. Table 3-2. Peripheral Functions Function Description...
- Page 12 AT32UC3L016/32/64 Table 3-4. Nexus OCD AUX Port Connections AXS=1 AXS=0 MDO[2] PA16 PB03 MDO[1] PA15 PB02 MDO[0] PA14 PB09 EVTO_N PA04 PA04 MCKO PA06 PB01 MSEO[1] PA07 PB11 MSEO[0] PA11 PB12 3.2.5 Oscillator Pinout The oscillators are not mapped to the normal GPIO functions and their muxings are controlled by registers in the System Control Interface (SCIF).
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Page 13: Signal Descriptions
AT32UC3L016/32/64 Signal Descriptions The following table gives details on signal name classified by peripheral. Table 3-7. Signal Descriptions List Active Signal Name Function Type Level Comments Analog Comparator Interface - ACIFB ACAN3 - ACAN0 Negative inputs for comparators "A" Analog ACAP3 - ACAP0 Positive inputs for comparators "A"... - Page 14 AT32UC3L016/32/64 Table 3-7. Signal Descriptions List Power Manager - PM RESET_N Reset Input Pulse Width Modulation Controller - PWMA PWMA35 - PWMA0 PWMA channel waveforms Output PWMAOD35 - PWMA channel waveforms, open drain Not all channels support open Output PWMAOD0 mode drain mode System Control Interface - SCIF...
- Page 15 AT32UC3L016/32/64 Table 3-7. Signal Descriptions List Clock Clear To Send Input Request To Send Output Receive Data Input Transmit Data Output Note: 1. ADCIFB: AD3 does not exist. Table 3-8. Signal Description List, continued Active Signal Name Function Type Level Comments Power Power...
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Page 16: I/O Line Considerations
AT32UC3L016/32/64 I/O Line Considerations 3.4.1 JTAG Pins The JTAG is enabled if TCK is low while the RESET_N pin is released. The TCK, TMS, and TDI pins have pull-up resistors when JTAG is enabled. The TCK pin always have pull-up enabled during reset. - Page 17 AT32UC3L016/32/64 the system to start other devices or to clock a switching regulator to rise the power supply volt- age up to an acceptable value. The clock will be available on PA20 until one of the following conditions are true: •PA20 is configured to use a GPIO function other than F (SCIF-RC32OUT) •PA20 is configured as a General Purpose Input/Output (GPIO) •The bit FRC32 in the Power Manager PPCR register is written to zero (refer to the Power...
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Page 18: Processor And Architecture
AT32UC3L016/32/64 4. Processor and Architecture Rev: 2.1.0.0 This chapter gives an overview of the AVR32UC CPU. AVR32UC is an implementation of the AVR32 architecture. A summary of the programming model, instruction set, and MPU is pre- sented. For further details, see the AVR32 Architecture Manual and the AVR32UC Technical Reference Manual. -
Page 19: The Avr32Uc Cpu
AT32UC3L016/32/64 The register file is organized as sixteen 32-bit registers and includes the Program Counter, the Link Register, and the Stack Pointer. In addition, register R12 is designed to hold return values from function calls and is used implicitly by some instructions. The AVR32UC CPU The AVR32UC CPU targets low- and medium-performance applications, and provides an advanced On-Chip Debug (OCD) system, no caches, and a Memory Protection Unit (MPU). - Page 20 AT32UC3L016/32/64 Figure 4-1. Overview of the AVR32UC CPU Power/ Reset system control AVR32UC CPU pipeline Data memory controller Instruction memory controller High High CPU Local Speed High Speed Bus master Speed CPU RAM Bus slave master master 4.3.1 Pipeline Overview AVR32UC has three pipeline stages, Instruction Fetch (IF), Instruction Decode (ID), and Instruc- tion Execute (EX).
- Page 21 AT32UC3L016/32/64 Figure 4-2. The AVR32UC Pipeline Multiply unit Regfile Regfile ALU unit Read write Prefetch unit Decode unit Load-store unit 4.3.2 AVR32A Microarchitecture Compliance AVR32UC implements an AVR32A microarchitecture. The AVR32A microarchitecture is tar- geted at cost-sensitive, lower-end applications like smaller microcontrollers. This microarchitecture does not provide dedicated hardware registers for shadowing of register file registers in interrupt contexts.
- Page 22 AT32UC3L016/32/64 address exception. Doubleword-sized accesses with word-aligned pointers will automatically be performed as two word-sized accesses. The following table shows the instructions with support for unaligned addresses. All other instructions require aligned addresses. Table 4-1. Instructions with Unaligned Reference Support Instruction Supported Alignment ld.d...
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Page 23: Programming Model
AT32UC3L016/32/64 Programming Model 4.4.1 Register File Configuration The AVR32UC register file is shown below. Figure 4-3. The AVR32UC Register File Supervisor INT0 INT1 INT2 INT3 Exception Secure Application Bit 31 Bit 0 Bit 31 Bit 0 Bit 31 Bit 0 Bit 31 Bit 0 Bit 31... - Page 24 AT32UC3L016/32/64 Figure 4-5. The Status Register Low Halfword Bit 15 Bit 0 Bit name Initial value Carry Zero Sign Overflow Saturation Lock Reserved Scratch Reserved 4.4.3 Processor States 4.4.3.1 Normal RISC State The AVR32 processor supports several different execution contexts as shown in Table 4-2.
- Page 25 AT32UC3L016/32/64 Debug state can be entered as described in the AVR32UC Technical Reference Manual. Debug state is exited by the retd instruction. 4.4.3.3 Secure State The AVR32 can be set in a secure state, that allows a part of the code to execute in a state with higher security levels.
- Page 26 AT32UC3L016/32/64 Table 4-3. System Registers (Continued) Reg # Address Name Function JAVA_LV1 Unused in AVR32UC JAVA_LV2 Unused in AVR32UC JAVA_LV3 Unused in AVR32UC JAVA_LV4 Unused in AVR32UC JAVA_LV5 Unused in AVR32UC JAVA_LV6 Unused in AVR32UC JAVA_LV7 Unused in AVR32UC JTBA Unused in AVR32UC JBCR Unused in AVR32UC...
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Page 27: Exceptions And Interrupts
AT32UC3L016/32/64 Table 4-3. System Registers (Continued) Reg # Address Name Function MPUPSR2 MPU Privilege Select Register region 2 MPUPSR3 MPU Privilege Select Register region 3 MPUPSR4 MPU Privilege Select Register region 4 MPUPSR5 MPU Privilege Select Register region 5 MPUPSR6 MPU Privilege Select Register region 6 MPUPSR7 MPU Privilege Select Register region 7... - Page 28 AT32UC3L016/32/64 relative to EVBA. The autovector offset has 14 address bits, giving an offset of maximum 16384 bytes. The target address of the event handler is calculated as (EVBA | event_handler_offset), not (EVBA + event_handler_offset), so EVBA and exception code segments must be set up appropriately.
- Page 29 AT32UC3L016/32/64 4.5.3 Supervisor Calls The AVR32 instruction set provides a supervisor mode call instruction. The scall instruction is designed so that privileged routines can be called from any context. This facilitates sharing of code between different execution modes. The scall mechanism is designed so that a minimal execution cycle overhead is experienced when performing supervisor routine calls from time- critical event handlers.
- Page 30 AT32UC3L016/32/64 than the oldest instruction. An instruction B is younger than an instruction A if it was sent down the pipeline later than A. The addresses and priority of simultaneous events are shown in Table 4-4 on page 31. Some of the exceptions are unused in AVR32UC since it has no MMU, coprocessor interface, or floating- point unit.
- Page 31 AT32UC3L016/32/64 Table 4-4. Priority and Handler Addresses for Events Priority Handler Address Name Event source Stored Return Address 0x80000000 Reset External input Undefined Provided by OCD system OCD Stop CPU OCD system First non-completed instruction EVBA+0x00 Unrecoverable exception Internal PC of offending instruction EVBA+0x04 TLB multiple hit PC of offending instruction...
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Page 32: Memories
• User Page For Data To Be Preserved During Chip Erase • Internal High-Speed SRAM, Single-cycle access at full speed – 16Kbytes (AT32UC3L064, AT32UC3L032) – 8Kbytes (AT32UC3L016) Physical Memory Map The system bus is implemented as a bus matrix. All system bus addresses are fixed, and they are never remapped in any way, not even in boot. -
Page 33: Peripheral Address Map
AT32UC3L016/32/64 Peripheral Address Map Table 5-3. Peripheral Address Mapping Address Peripheral Name 0xFFFE0000 FLASHCDW Flash Controller - FLASHCDW 0xFFFE0400 HMATRIX HSB Matrix - HMATRIX 0xFFFE0800 Secure Access Unit - SAU 0xFFFF0000 PDCA Peripheral DMA Controller - PDCA 0xFFFF1000 INTC Interrupt controller - INTC 0xFFFF1400 Power Manager - PM 0xFFFF1800... -
Page 34: Cpu Local Bus Mapping
AT32UC3L016/32/64 Table 5-3. Peripheral Address Mapping 0xFFFF4800 TWIM1 Two-wire Master Interface - TWIM1 0xFFFF4C00 TWIS0 Two-wire Slave Interface - TWIS0 0xFFFF5000 TWIS1 Two-wire Slave Interface - TWIS1 0xFFFF5400 PWMA Pulse Width Modulation Controller - PWMA 0xFFFF5800 Timer/Counter - TC0 0xFFFF5C00 Timer/Counter - TC1 0xFFFF6000 ADCIFB... - Page 35 AT32UC3L016/32/64 The following GPIO registers are mapped on the local bus: Table 5-4. Local Bus Mapped GPIO Registers Local Bus Port Register Mode Address Access Output Driver Enable Register (ODER) WRITE 0x40000040 Write-only 0x40000044 Write-only CLEAR 0x40000048 Write-only TOGGLE 0x4000004C Write-only Output Value Register (OVR) WRITE...
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Page 36: Supply And Startup Considerations
AT32UC3L016/32/64 6. Supply and Startup Considerations Supply Considerations 6.1.1 Power Supplies The AT32UC3L has several types of power supply pins: •VDDIO: Powers I/O lines. Voltage is 1.8 to 3.3V nominal. •VDDIN: Powers I/O lines and the internal regulator. Voltage is 1.8 to 3.3V nominal. •VDDANA: Powers the ADC. - Page 37 AT32UC3L016/32/64 6.1.3.1 3.3V Single Supply Mode In 3.3V single supply mode the internal regulator is connected to the 3.3V source (VDDIN pin) and its output feeds VDDCORE. Figure 6-2 shows the power schematics to be used for 3.3V sin- gle supply mode. All I/O lines will be powered by the same power (VDDIN=VDDIO). Figure 6-2.
- Page 38 AT32UC3L016/32/64 6.1.3.2 1.8V Single Supply Mode In 1.8V single supply mode the internal regulator is not used, and VDDIO and VDDCORE are powered by a single 1.8V supply as shown in Figure 6-3. All I/O lines will be powered by the same power (VDDIN = VDDIO = VDDCORE).
- Page 39 AT32UC3L016/32/64 6.1.3.3 3.3V Supply Mode with 1.8V Regulated I/O Lines In this mode, the internal regulator is connected to the 3.3V source and its output is connected to both VDDCORE and VDDIO as shown in Figure 6-4. This configuration is required in order to use Shutdown mode.
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Page 40: Startup Considerations
AT32UC3L016/32/64 6.1.4 Power-up Sequence 6.1.4.1 Maximum Rise Rate To avoid risk of latch-up, the rise rate of the power supplies must not exceed the values described in Table 7-3 on page Recommended order for power supplies is also described in this chapter. 6.1.4.2 Minimum Rise Rate The integrated Power-Reset circuitry monitoring the VDDIN powering supply requires a mini-... -
Page 41: Electrical Characteristics
AT32UC3L016/32/64 7. Electrical Characteristics Disclaimer All values in this chapter are preliminary and subject to change without further notice. Absolute Maximum Ratings* Table 7-1. Absolute Maximum Ratings *NOTICE: Stresses beyond those listed under Operating temperature........-40°C to +85°C “Absolute Maximum Ratings” may cause Storage temperature........ -
Page 42: Maximum Clock Frequencies
AT32UC3L016/32/64 Table 7-3. Supply Rise Rates and Order Rise Rate Symbol Parameter Unit Comment DC supply peripheral I/Os V/µs VDDIO DC supply peripheral I/Os 0.002 V/µs VDDIN and internal regulator Rise before or at the same DC supply core V/µs VDDCORE time as VDDIO Rise together with... - Page 43 AT32UC3L016/32/64 – OSC0 (crystal oscillator) stopped – OSC32K (32KHz crystal oscillator) running with external 32KHz crystal – DFLL running at 50MHz with OSC32K as reference • Clocks – DFLL used as main clock source – CPU, HSB, and PBB clocks undivided –...
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Page 44: I/O Pad Characteristics
AT32UC3L016/32/64 Figure 7-1. Measurement Schematic, Internal Core Supply VDDIN Amp0 VDDIO VDDCORE VDDANA Figure 7-2. Measurement Schematic, External Core Supply VDDIN Amp0 VDDIO VDDCORE VDDANA I/O Pad Characteristics Table 7-6. Normal I/O Pad Characteristics Symbol Parameter Condition Units Pull-up resistance kOhm PULLUP = 3.0V... - Page 45 AT32UC3L016/32/64 Table 7-6. Normal I/O Pad Characteristics Symbol Parameter Condition Units = 3.0V, I = 3mA Output low-level voltage = 1.62 V, I = 2mA = 3.0V, I = 3mA - 0.4 Output high-level voltage = 1.62 V, I = 2mA - 0.4 Input leakage current Pull-up resistors disabled...
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Page 46: Oscillator Characteristics
AT32UC3L016/32/64 Table 7-9. 5V Tolerant High-drive I/O Pad Characteristics Symbol Parameter Condition Units Pull-up resistance kOhm PULLUP = 3.0V -0.3 0.3*V Input low-level voltage = 1.62V -0.3 0.3*V = 3.6V 0.7*V Input high-level voltage = 1.98V 0.7*V = 3.0V, I = 6mA Output low-level voltage = 1.62 V, I... - Page 47 AT32UC3L016/32/64 7.7.1.2 Crystal Oscillator Characteristics The following table describes the characteristics for the oscillator when a crystal is connected between XIN and XOUT as shown in Figure 7-3. The user must choose a crystal oscillator where the crystal load capacitance is within the range given in the table.
- Page 48 AT32UC3L016/32/64 Table 7-13. 32 KHz Crystal Oscillator Characteristics Symbol Parameter Conditions Unit Internal equicalent load capacitance Current consumption µA Equivalent series resistance 32 768Hz kOhm Note: 1. Nominal crystal cycles. 7.7.3 Digital Frequency Locked Loop (DFLL) Characteristics Table 7-14. Digital Frequency Locked Loop Characteristics Symbol Parameter Conditions...
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Page 49: Flash Characteristics
AT32UC3L016/32/64 7.7.4 120MHz RC Oscillator (RC120M) Characteristics Table 7-15. Internal 120MHz RC Oscillator Characteristics Symbol Parameter Conditions Unit Output frequency T = 25°C, V = 1.8V VDDCORE Temperature drift +/-5 Duty Duty cycle 7.7.5 32kHz RC Oscillator (RC32K) Characteristics Table 7-16. 32kHz RC Oscillator Characteristics Symbol Parameter... -
Page 50: Analog Characteristics
AT32UC3L016/32/64 Table 7-20. Flash Endurance and Data Retention Symbol Parameter Conditions Unit Array endurance (write/page) 100k cycles FARRAY General Purpose fuses endurance (write/bit) cycles FFUSE Data retention years Analog Characteristics 7.9.1 Voltage Regulator Characteristics 7.9.1.1 Electrical Characteristics Table 7-21. Electrical Characteristics Symbol Parameter Condition... - Page 51 AT32UC3L016/32/64 7.9.2 ADC Characteristics Table 7-23. Channel Conversion Time and ADC Clock Symbol Parameter Conditions Units 10-bit resolution mode ADC clock frequency 8-bit resolution mode Startup time Return from Idle Mode µs STARTUP Sample and hold acquisition time Conversion time (latency) = 6MHz cycles CONV...
- Page 52 AT32UC3L016/32/64 Table 7-27. Transfer Characteristics 8-bit Resolution Mode Parameter Conditions Units Integral non-linearity +/-0.5 Differential non-linearity -0.23 0.25 ADC clock frequency = 6MHz Offset error +/-1 Gain error +/-1 7.9.3 Analog Comparator Characteristics Table 7-28. Analog Comparator Characteristics Symbol Parameter Condition Units Positive input voltage range...
- Page 53 AT32UC3L016/32/64 7.9.4 POR18 Table 7-29. Power-on Reset Characteristics Symbol Parameter Condition Units Voltage threshold on V rising T=25°C 1.45 POT+ VDDCORE Voltage threshold on V falling T=25°C 1.32 POT- VDDCORE Figure 7-4. POR18 Operating Principles POT+ POT- 32099DS–06/2010...
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Page 54: Timing Characteristics
AT32UC3L016/32/64 7.9.5 POR33 Table 7-30. POR33 Characteristics Symbol Parameter Condition Units Voltage threshold on V rising 1.49 POT+ VDDIN T=25°C Voltage threshold on V falling 1.45 POT- VDDIN Figure 7-5. POR33 Operating Principles POT+ POT- 7.9.6 Temperature Sensor Table 7-31. Temperature Sensor Characteristics Symbol Parameter... -
Page 55: Mechanical Characteristics
AT32UC3L016/32/64 8. Mechanical Characteristics Thermal Considerations 8.1.1 Thermal Data Table 8-1 summarizes the thermal resistance data depending on the package. Table 8-1. Thermal Resistance Data Symbol Parameter Condition Package Unit θ Junction-to-ambient thermal resistance Still Air TQFP48 63.2 °C/W θ Junction-to-case thermal resistance TQFP48 21.8... -
Page 56: Package Drawings
AT32UC3L016/32/64 Package Drawings Figure 8-1. TQFP-48 Package Drawing Table 8-2. Device and Package Maximum Weight Table 8-3. Package Characteristics Moisture Sensitivity Level MSL3 Table 8-4. Package Reference JEDEC Drawing Reference MS-026 JESD97 Classification 32099DS–06/2010... - Page 57 AT32UC3L016/32/64 Figure 8-2. QFN-48 Package Drawing Note: The exposed pad is not connected to anything. Table 8-5. Device and Package Maximum Weight Table 8-6. Package Characteristics Moisture Sensitivity Level MSL3 Table 8-7. Package Reference JEDEC Drawing Reference M0-220 JESD97 Classification 32099DS–06/2010...
- Page 58 AT32UC3L016/32/64 Figure 8-3. TLLGA-48 Package Drawing Table 8-8. Device and Package Maximum Weight 39.3 Table 8-9. Package Characteristics Moisture Sensitivity Level MSL3 Table 8-10. Package Reference JEDEC Drawing Reference M0-220 JESD97 Classification 32099DS–06/2010...
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Page 59: Soldering Profile
AT32UC3L016/32/64 Soldering Profile Table 8-11 gives the recommended soldering profile from J-STD-20. Table 8-11. Soldering Profile Profile Feature Green Package Average Ramp-up Rate (217°C to Peak) 3°C/s max Preheat Temperature 175°C ±25°C 150-200°C Time Maintained Above 217°C 60-150 s Time within 5°C of Actual Peak Temperature 30 s Peak Temperature Range 260°C... -
Page 60: Ordering Information
AT32UC3L016/32/64 9. Ordering Information Table 9-1. Ordering Information Temperature Operating Device Ordering Code Carrier Type Package Package Type Range AT32UC3L064-AUTES AT32UC3L064-AUT Tray TQFP 48 AT32UC3L064-AUR Tape & Reel JESD97 Classification E3 AT32UC3L064-ZAUES AT32UC3L064 AT32UC3L064-ZAUT Tray QFN 48 AT32UC3L064-ZAUR Tape & Reel... -
Page 61: Errata
AT32UC3L016/32/64 10. Errata 10.1 Rev. E 10.1.1 Processor and Architecture 1. Privilege violation when using interrupts in application mode with protected system stack If the system stack is protected by the MPU and an interrupt occurs in application mode, an MPU DTLB exception will occur. - Page 62 AT32UC3L016/32/64 Solution 2: Only turn off the CFD while running the main clock on RCSYS. 10.1.4 SCIF 1. PCLKSR.OSC32RDY bit might not be cleared after disabling OSC32K In some cases the OSC32RDY bit in the PCLKSR register will not be cleared when OSC32K is disabled.
- Page 63 AT32UC3L016/32/64 10.1.8 1. SPI disable does not work in SLAVE mode SPI disable does not work in SLAVE mode. Fix/Workaround Read the last received data, then perform a software reset by writing a one to the Software Reset bit in the Control Register (CR.SWRST). 2.
- Page 64 AT32UC3L016/32/64 10.1.10 PWMA 1. BUSY bit is never cleared after writes to the Control Register (CR) When writing a non-zero value to CR.TOP, CR.SPREAD, or CR.TCLR when the PWMA is disabled (CR.EN==0), the BUSY bit in the Status Register (SR.BUSY) will be set, but never cleared.
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Page 65: Rev. D
AT32UC3L016/32/64 10.2 Rev. D 10.2.1 Processor and Architecture 1. Privilege violation when using interrupts in application mode with protected system stack If the system stack is protected by the MPU and an interrupt occurs in application mode, an MPU DTLB exception will occur. Fix/Workaround Make a DTLB Protection (Write) exception handler which permits the interrupt request to be handled in privileged mode. - Page 66 AT32UC3L016/32/64 - When entering Shutdown mode while debugging the chip using JTAG or aWire interface. In the listed cases, writing a one to the bit VREGCR.POR33MASK in the System Control Interface (SCIF) to mask the POR33 reset will be ineffective. Fix/Workaround - Do not disable POR33 using the user interface.
- Page 67 AT32UC3L016/32/64 10.2.6 1. Clearing the Watchdog Timer (WDT) counter in second half of timeout period will issue a Watchdog reset If the WDT counter is cleared in the second half of the timeout period, the WDT will immedi- ately issue a Watchdog reset. Fix/Workaround Use twice as long timeout period as needed and clear the WDT counter within the first half of the timeout period.
- Page 68 AT32UC3L016/32/64 5. SPI mode fault detection enable causes incorrect behavior When mode fault detection is enabled (MR.MODFDIS==0), the SPI module may not operate properly. Fix/Workaround Always disable mode fault detection before using the SPI by writing a one to MR.MODFDIS. 10.2.9 1.
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Page 69: Rev. C
AT32UC3L016/32/64 2. The aWire debug interface is reset after leaving Shutdown mode If the aWire debug mode is used as debug interface and the program enters Shutdown mode, the aWire interface will be reset when the device receives a wakeup either from the WAKE_N pin or the AST. - Page 70 AT32UC3L016/32/64 Hardware breakpoints on MAC instructions may corrupt the destination register of the MAC instruction. Fix/Workaround Place breakpoints on earlier or later instructions. 3. RETS behaves incorrectly when MPU is enabled RETS behaves incorrectly when MPU is enabled and MPU is configured so that system stack is not readable in unprivileged mode.
- Page 71 AT32UC3L016/32/64 10.4.3 HMATRIX 1. In the PRAS and PRBS registers, the MxPR fields are only two bits In the PRAS and PRBS registers MxPR fields are only two bits wide, instead of four bits. The unused bits are undefined when reading the registers. Fix/Workaround Mask undefined bits when reading PRAS and PRBS.
- Page 72 AT32UC3L016/32/64 Before going to sleep modes where RCSYS is stopped, make sure the division factor between the CPU/HSB and PBx frequencies is less than or equal to 4. 2. Disabling POR33 may generate spurious resest Depending on operating conditions, POR33 may generate a spurious reset in one of the fol- lowing cases: - When POR33 is disabled from the user interface.
- Page 73 AT32UC3L016/32/64 If all the following operating conditions are true, exiting sleep walking might lead to instability: -The OSC0 is enabled in external clock mode (OSCCTRL0.OSCEN == 1 and OSCCTRL0.MODE == 0) -A sleep mode where the OSC0 is automatically disabled is entered -The chip enters sleep walking Fix/Workaround Do not run OSC0 in external clock mode if sleep walking is expected to be used.
- Page 74 AT32UC3L016/32/64 8. Generic clock sources are kept running in sleep modes If a clock is used as a source for a generic clock when going to a sleep mode where clock sources are stopped, the source of the generic clock will be kept running. Please refer to the Power Manager chapter for details about sleep modes.
- Page 75 AT32UC3L016/32/64 None. 18. GCLK5 is non-functional GCLK5 is non-functional. Fix/Workaround None. 19. DFLLIF might loose fine lock when dithering is disabled When dithering is disabled, and fine lock has been acquired the DFLL might loose the fine lock resulting in a up to 20% over-/undershoot. Fix/Workaround Solution 1: When the DFLL is used as main clock source the target frequency of the DFLL should be 20% below the maximum operating frequency of the CPU.
- Page 76 AT32UC3L016/32/64 If the WDT counter is cleared in the second half of the timeout period, the WDT will immedi- ately issue a Watchdog reset. Fix/Workaround Use twice as long timeout period as needed and clear the WDT counter within the first half of the timeout period.
- Page 77 AT32UC3L016/32/64 Read the last received data, then perform a software reset by writing a one to the Software Reset bit in the Control Register (CR.SWRST). 2. SPI Bad Serial Clock Generation on 2nd chip select when SCBR==1, CPOL==1, and NCPHA==0 W h e n m u l t i p l e c h i p s e l e c t s a r e i n u s e , i f o n e o f t h e b a u d r a t e s i s e q u a l t o 1 (CSRn.SCBR==1) and one of the others is not equal to 1, and CSRn.CPOL==1 and CSRn.NCPHA==0, an additional pulse will be generated on SCK.
- Page 78 AT32UC3L016/32/64 The TWI pins draws current when the pins are supplied with 3.3 V and the part is left unpowered. Fix/Workaround None. 5. PA21, PB04, and PB05 are not 5V tolerant Pins PA21, PB04, and PB05 are only 3.3V tolerant, not 5V tolerant. Fix/Workaround None.
- Page 79 AT32UC3L016/32/64 Fix/Workaround None. 3. VERSION register reads 0x100 The VERSION register reads 0x100 instead of 0x101. Fix/Workaround None. 4. Writing to the duty cycle registers when the timebase counter overflows can give an undefined result The duty cycle registers will be corrupted if written when the timebase counter overflows. If the duty cycle registers are written exactly when the timebase counter overflows at TOP, the duty cycle registers may become corrupted.
- Page 80 AT32UC3L016/32/64 3. ADC channels six to eight are non-functional ADC channels six to eight are non-functional. Fix/Workaround None. 4. VERSION register reads 0x100 The VERSION register reads 0x100 instead of 0x101. Fix/Workaround None. 10.4.18 ACIFB 1. Negative offset The static offset of the analog comparator is appriximately -50mV. Fix/Workaround None.
- Page 81 AT32UC3L016/32/64 None. 4. MGCFG2.ACCTRL bit is stuck at zero The ACCTRL bit in the MGCFG2 register is stuck at zero and cannot be written to one. The analog comparators will be constantly enabled. Fix/Workaround None. 5. MGCFG2.CONSEN field is stuck at zero The CONSEN field in the MGCFG2 register is stuck at zero and cannot be written to a differ- ent value.
- Page 82 AT32UC3L016/32/64 aWire enable does not work in Static mode. Fix/Workaround None. 5. VERSION register reads 0x200 The VERSION register reads 0x200 instead of 0x210. Fix/Workaround None. 6. The aWire debug interface is reset after leaving Shutdown mode If the aWire debug mode is used as debug interface and the program enters Shutdown mode, the aWire interface will be reset when the device receives a wakeup either from the WAKE_N pin or the AST.
- Page 83 AT32UC3L016/32/64 Do not enter Shutdown mode. Fix/Workaround None. 3. VDDIN current consumption increase above 1.8V When VDDIN increases above 1.8V, current on VDDIN increases with up to 40µA. Fix/Workaround None. 4. Increased Power Consumption in VDDIO in sleep modes If the OSC0 is enabled in crystal mode when entering a sleep mode where the OSC0 is dis- abled, this will lead to an increased power consumption in VDDIO.
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Page 84: Datasheet Revision History
Please note that the referring page numbers in this section are referred to this document. The referring revision in this section are referring to the document revision. 11.1 Rev. D - 06/2010 Ordering Information: Ordering code for TQFP ES changed from AT32UC3L064-AUES to AT32UC3L064-AUTES. TLLGA48 Tray option added. 11.2 Rev. C - 06/2010 Features and Description: Added QTouch library support. -
Page 85: Rev. A - 06/2009
AT32UC3L016/32/64 SPI: RDR.PCS field removed (RDR[19:16]). TWIS: Figures updated. ADCIFB: The sample and hold time and the startup time formulas have been corrected (ADC Configuration Register). ADCIFB: Updated ADC signal names. ACIFB: CONFW.WEVSRC is bit 8-10, CONFW.EWEVEN is bit 11. CONF.EVENP and CONF.EVENN bits are swapped. -
Page 86: Table Of Contents
AT32UC3L016/32/64 Table of Contents Features ..................... 1 Description ....................3 Overview ....................5 Block Diagram ....................5 Configuration Summary ..................6 Package and Pinout ................. 7 Package ......................7 Peripheral Multiplexing on I/O lines ..............9 Signal Descriptions ..................13 I/O Line Considerations ...................16 Processor and Architecture ..............18 Features ......................18 AVR32 Architecture ..................18 The AVR32UC CPU ..................19... - Page 87 AT32UC3L016/32/64 Flash Characteristics ..................49 Analog Characteristics ..................50 7.10 Timing Characteristics ..................54 Mechanical Characteristics ..............55 Thermal Considerations ..................55 Package Drawings ...................56 Soldering Profile ....................59 Ordering Information ................60 10 Errata ....................... 61 10.1 Rev. E ......................61 10.2 Rev. D ......................65 10.3 Rev.
- Page 88 Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI- TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY...