Page 1 • On-chip Expanded RAM (ERAM): 1024 Bytes • Integrated Power Monitor (POR/PFD) to Supervise Internal Power Supply AT89C5130A-M • USB 1.1 and 2.0 Full Speed Compliant Module with Interrupt on Transfer Completion – Endpoint 0 for Control Transfers: 32-byte FIFO AT89C5131A-M –...
Page 2: Description
(EP1/EP2/EP3/EP4/EP5/EP6) with minimum software overhead are also part of the USB module. AT89C5130A/31A-M retains the features of the Atmel 80C52 with extended Flash capacity (16/32-Kbytes), 256 bytes of internal RAM, a 4-level interrupt system, two 16-bit timer/counters (T0/T1), a full duplex enhanced UART (EUART) and an on-chip oscillator.
Page 3: Block Diagram
AT89C5130A/31A-M 2. Block Diagram (1) (1) (1) (1) (1) (1) (3) (3) XTAL1 ERAM XTAL2 EEPROM EUART 16/32Kx8Flash 1Kx8 4Kx8 Timer2 256x8 CORE PSEN Parallel I/O Ports & Ext. Bus Timer 0 Watch Regu- Ctrl Timer 1 Board lator VREF Port 0Port 1 Port 2 Port 3 Port 4 (2) (2)
Page 4: Pinout Description
3. Pinout Description Pinout Figure 3-1. AT89C5130A/31A-M 52-pin PLCC Pinout 5 4 3 2 1 52 51 50 49 48 P4.1/SDA P2.3/A11 P0.1/AD1 P2.4/A12 P0.2/AD2 P2.5/A13 P0.3/AD3 XTAL2 XTAL1 PLCC52 P2.6/A14 P0.4/AD4 P2.7/A15 P3.7/RD/LED3 P0.5/AD5 AVDD P0.6/AD6 UCAP P0.7/AD7 AVSS P3.6/WR/LED2 P3.0/RxD 21 22...
Page 5 AT89C5130A/31A-M Figure 3-2. AT89C5130A/31A-M 64-pin VQFP Pinout 62 61 60 59 58 57 56 55 54 53 51 50 49 P2.3/A11 P2.4/A12 P0.1/AD1 P2.5/A13 P0.2/AD2 XTAL2 XTAL1 P0.3/AD3 P2.6/A14 P2.7/A15 VQFP64 P0.4/AD4 AVDD P3.7/RD/LED3 UCAP P0.5/AD5 AVSS P0.6/AD6 P0.7/AD7 P3.0/RxD P3.6/WR/LED2 17 18 26 27...
Page 6: Signals
Figure 3-3. AT89C5130A/31A-M 32-pin QFN Pinout 32 31 30 29 28 27 26 25 P4.1/SDA P1.0/T2/KIN0 XTAL2 XTAL1 QFN32 UCAP AVSS P3.7/RD/LED3 P3.0/RxD P3.6/WR/LED2 PLLF P3.5/T1/LED1 9 10 11 12 13 14 15 16 Note : The metal plate can be connected to Vss Signals All the AT89C5130A/31A-M signals are detailed by functionality on Table 3-1 through Table 3- Table 3-1.
Page 7 AT89C5130A/31A-M Signal Alternate Name Type Description Function P1.3 Capture External Input P1.4 CEX[4:0] P1.5 Compare External Output P1.6 P1.7 Table 3-3. Serial I/O Signal Description Signal Alternate Name Type Description Function Serial Input Port P3.0 Serial Output Port P3.1 Table 3-4. Timer 0, Timer 1 and Timer 2 Signal Description Signal Alternate...
Page 8 Table 3-5. LED Signal Description Signal Alternate Name Type Description Function Direct Drive LED Output P3.3 These pins can be directly connected to the Cathode of standard LEDs P3.5 LED[3:0] without external current limiting resistors. The typical current of each P3.6 output can be programmed by software to 2, 6 or 10 mA.
Page 9 AT89C5130A/31A-M Table 3-8. Ports Signal Description Signal Name Type Description Alternate Function Port 0 P0 is an 8-bit open-drain bidirectional I/O port. Port 0 pins that have 1s written to them float and can be used P0[7:0] AD[7:0] as high impedance inputs. To avoid any parasitic current consumption, Floating P0 inputs must be pulled to V KIN[7:0] Port 1...
Page 10 Table 3-10. USB Signal Description Signal Alternate Name Type Description Function USB Data + signal Set to high level under reset. USB Data - signal Set to low level under reset. USB Reference Voltage VREF Connect this pin to D+ using a 1.5 kΩ resistor to use the Detach function. Table 3-11.
Page 11 AT89C5130A/31A-M Table 3-12. Power Signal Description (Continued) Signal Alternate Name Type Description Function Analog Supply Voltage AVDD AVDD is used to supply the on-chip PLL and the USB PAD. Digital Ground VSS is used to supply the buffer ring and the digital core. USB Digital Ground UVSS UVSS is used to supply the USB pads.
Page 12: Typical Application
4. Typical Application Recommended External components All the external components described in the figure below must be implemented as close as pos- sible from the microcontroller package. The following figure represents the typical wiring schematic. Figure 4-1. Typical Application 100nF 100nF 4.7µF 1.5K...
Page 13: Pcb Recommandations
AT89C5130A/31A-M PCB Recommandations Figure 4-2. USB Pads Components must be Wires must be routed in Parallel and close to the must be as short as possible microcontroller VRef USB Connector If possible, isolate D+ and D- signals from other signals with ground wires Figure 4-3.
Page 14: Clock Controller
5. Clock Controller Introduction The AT89C5130A/31A-M clock controller is based on an on-chip oscillator feeding an on-chip Phase Lock Loop (PLL). All the internal clocks to the peripherals and CPU core are generated by this controller. The AT89C5130A/31A-M X1 and X2 pins are the input and the output of a single-stage on-chip inverter (see Figure 5-1) that can be configured with off-chip components as a Pierce oscillator (see Figure 5-2).
Page 15: Pll
AT89C5130A/31A-M In order to optimize the power consumption, the oscillator inverter is inactive when the PLL out- put is not selected for the USB device. Figure 5-2. Crystal Connection 5.3.1 PLL Description The AT89C5130A/31A-M PLL is used to generate internal high frequency clock (the USB Clock) synchronized with an external low-frequency (the Peripheral Clock).
Page 16 Figure 5-4. PLL Filter Connection PLLF The typical values are: R = 100 Ω, C1 = 10 nf, C2 = 2.2 nF. 5.3.2 PLL Programming The PLL is programmed using the flow shown in Figure 5-5. As soon as clock generation is enabled user must wait until the lock indicator is set to ensure the clock output is stable.
Page 17: Registers
AT89C5130A/31A-M Oscillator Frequency PLLDIV 32 MHz 40 MHz Registers Table 5-2. CKCON0 (S:8Fh) Clock Control Register 0 TWIX2 WDX2 PCAX2 SIX2 T2X2 T1X2 T0X2 Bit Number Mnemonic Description TWI Clock This control bit is validated when the CPU clock X2 is set. When X2 is low, TWIX2 this bit has no effect.
Page 18 Reset Value = 0000 0000b Table 5-3. CKCON1 (S:AFh) Clock Control Register 1 SPIX2 Bit Number Mnemonic Description Reserved The value read from this bit is always 0. Do not set this bit. SPI Clock This control bit is validated when the CPU clock X2 is set. When X2 is low, SPIX2 this bit has no effect.
Page 19 AT89C5130A/31A-M Bit Number Mnemonic Description R3:0 PLL R Divider Bits N3:0 PLL N Divider Bits Reset Value = 0000 0000 4337K–USB–04/08...
Page 20: Sfr Mapping
6. SFR Mapping The Special Function Registers (SFRs) of the AT89C5130A/31A-M fall into the following categories: • C51 core registers: ACC, B, DPH, DPL, PSW, SP • I/O port registers: P0, P1, P2, P3, P4 • Timer registers: T2CON, T2MOD, TCON, TH0, TH1, TH2, TMOD, TL0, TL1, TL2, RCAP2L, RCAP2H •...
Page 21 AT89C5130A/31A-M The table below shows all SFRs with their address and their reset value. Table 6-1. SFR Descriptions Addressable Non-Bit Addressable CCAP0H CCAP1H CCAP2H CCAP3H CCAP4H UEPINT 0000 0000 0000 0000 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX LEDCON 0000 0000 0000 0000...
Page 22 The Special Function Registers (SFRs) of the AT89C5131 fall into the following categories: Table 6-2. C51 Core SFRs Mnemonic Name Accumulator B Register Program Status Word Stack Pointer LSB of SPX Data Pointer Low byte LSB of DPTR Data Pointer High byte MSB of DPTR Table 6-3.
Page 23 AT89C5130A/31A-M Table 6-4. Timer SFR’s (Continued) Mnemonic Name Timer/Counter 2 RCAP2H Reload/Capture High byte Timer/Counter 2 RCAP2L Reload/Capture Low byte WDTRST WatchDog Timer Reset WDTPRG WatchDog Timer Program Table 6-5. Serial I/O Port SFR’s Mnemonic Name SCON Serial Control FE/SM0 SBUF Serial Data Buffer SADEN...
Page 24 Table 6-7. PCA SFR’s Mnemo- Name CCAP0 PCA Compare Capture Module 0 CCAP1 PCA Compare Capture Module 1 CCAP0H7 CCAP0H6 CCAP0H5 CCAP0H4 CCAP0H3 CCAP0H2 CCAP0H1 CCAP0H0 CCAP1H7 CCAP1H6 CCAP1H5 CCAP1H4 CCAP1H3 CCAP1H2 CCAP1H1 CCAP1H0 CCAP2 PCA Compare Capture Module 2 CCAP2H7 CCAP2H6 CCAP2H5...
Page 25 AT89C5130A/31A-M Table 6-10. Keyboard SFRs Mnemonic Name Keyboard Level KBLS KBLS7 KBLS6 KBLS5 KBLS4 KBLS3 KBLS2 KBLS1 KBLS0 Selector Register Table 6-11. TWI SFRs Mnemonic Name Synchronous Serial SSCON SSIE Control Synchronous Serial SSCS Control-Status Synchronous Serial SSDAT Data Synchronous Serial SSADR Address Table 6-12.
Page 26 Table 6-13. USB SFR’s Mnemonic Name USB Byte Counter Low UBYCTLX BYCT7 BYCT6 BYCT5 BYCT4 BYCT3 BYCT2 BYCT1 BYCT0 (EP X) USB Byte Counter High UBYCTHX BYCT10 BYCT9 BYCT8 (EP X) USB Frame Number UFNUML FNUM7 FNUM6 FNUM5 FNUM4 FNUM3 FNUM2 FNUM1 FNUM0...
Page 27: Dual Data Pointer Register
AT89C5130A/31A-M 7. Dual Data Pointer Register The additional data pointer can be used to speed up code execution and reduce code size. The dual DPTR structure is a way by which the chip will specify the address of an external data memory location.
Page 28 ASSEMBLY LANGUAGE ; Block move using dual data pointers ; Modifies DPTR0, DPTR1, A and PSW ; note: DPS exits opposite of entry state ; unless an extra INC AUXR1 is added 00A2 AUXR1 EQU 0A2H 0000 909000MOV DPTR,#SOURCE ; address of SOURCE 0003 05A2 INC AUXR1 ;...
Page 29: Program/Code Memory
AT89C5130A/31A-M 8. Program/Code Memory The AT89C5130A/31A-M implement 16/ 32 Kbytes of on-chip program/code memory. Figure 8- 1 shows the split of internal and external program/code memory spaces depending on the product. The Flash memory increases EPROM and ROM functionality by in-circuit electrical erasure and programming.
Page 30 Figure 8-2. External Code Memory Interface Structure Flash AT89C5130A EPROM AT89C5131 A15:8 A15:8 AD7:0 Latch A7:0 A7:0 D7:0 PSEN Table 8-1. External Data Memory Interface Signals Signal Alternate Name Type Description Function Address Lines A15:8 P2.7:0 Upper address lines for the external bus. Address/Data Lines AD7:0 P0.7:0...
Page 31: Flash Memory Architecture
AT89C5130A/31A-M Flash Memory Architecture AT89C5130A/31A-M features two on-chip Flash memories: • Flash memory FM0: containing 32 Kbytes of program memory (user space) organized into 128-byte pages, • Flash memory FM1: 3 Kbytes for bootloader and Application Programming Interfaces (API). The FM0 supports both parallel programming and Serial In-System Programming (ISP) whereas FM1 supports only parallel programming by programmers.
Page 32: Overview Of Fm0 Operations
8.2.1.4 Column Latches The column latches, also part of FM0, have a size of full page (128 bytes). The column latches are the entrance buffers of the three previous memory locations (user array, XRow and Hardware security byte). Overview of FM0 Operations The CPU interfaces to the Flash memory through the FCON register and AUXR1 register.
Page 33 AT89C5130A/31A-M Table 8-3. Programming Spaces Write to FCON FPL3:0 FMOD1 FMOD0 Operation No action User Write the column latches in user space No action Extra Row Write the column latches in extra row space No action Security Space Write the fuse bits space No action Reserved No action...
Page 34 Figure 8-5. Column Latches Loading Procedure Column Latches Loading Column Latches Mapping FPS = 1 Data Load DPTR = Address ACC = Data Exec: MOVX @DPTR, A Last Byte to load? Data memory Mapping FPS = 0 8.3.6 Programming the Flash Spaces 8.3.6.1 User The following procedure is used to program the User space and is summarized in Figure 8-6:...
Page 35 AT89C5130A/31A-M Figure 8-6. Flash and Extra Row Programming Procedure Flash Spaces Programming Column Latches Loading see Figure 8-5 Disable IT EA = 0 Launch Programming FCON = 5xh FCON = Axh FBusy Cleared? Erase Mode FCON = 00h End Programming Enable IT EA = 1 8.3.6.3...
Page 36 Figure 8-7. Hardware Programming Procedure Flash Spaces Programming FCON = 0Ch Data Load DPTR = 00h ACC = Data Exec: MOVX @DPTR, A Disable IT EA = 0 Launch Programming FCON = 54h FCON = A4h FBusy Cleared? Erase Mode FCON = 00h End Programming Enable IT...
Page 37: Registers
AT89C5130A/31A-M 8.3.7.3 Hardware Security The following procedure is used to read the Hardware Security space and is summarized in Figure 8-8: • Map the Hardware Security space by writing 04h in FCON register. • Read the byte in Accumulator by executing MOVC A, @A+DPTR with A = 0 & DPTR = 0000h.
Page 38: Flash Eeprom Memory
9. Flash EEPROM Memory General Description The Flash memory increases EPROM functionality with in-circuit electrical erasure and program- ming. It contains 16/32 Kbytes of program memory organized in 128/256 pages of 128 bytes, respectively. This memory is both parallel and serial In-System Programmable (ISP). ISP allows devices to alter their own program memory in the actual end product under software control.
Page 39: Flash Registers And Memory Map
AT89C5130A/31A-M Flash Registers and Memory Map The AT89C5130A/31A-M Flash memory uses several registers: • Hardware register can be accessed with a parallel programmer.Some bits of the hardware register can be changed, also, by API (i.e. X2 and BLJB bits of Hardware security Byte) or ISP.
Page 40 Software Registers Several registers are used, in factory and by parallel programmers, to make copies of hardware registers contents. These values are used by Atmel ISP (see Section “In-System Programming (ISP)”). These registers are in the “Extra Flash Memory” part of the Flash memory. This block is also called ”XAF”...
Page 41 Software Boot Vector – Boot Status Byte 0FFh – Software Security Byte – Copy of the Manufacturer – Atmel Code Copy of the Device ID #1: C51 X2, Electrically – Family Code Erasable Copy of the Device ID #2: AT89C5130A/31A-M 32 –...
Page 42: Flash Memory Status
AT89C5130A/31A-M parts are delivered with the ISP boot in the Flash memory. After ISP or par- allel programming, the possible contents of the Flash memory are summarized in Figure 9-1: Figure 9-1. Flash Memory Possible Contents 3FFFh AT89C5130A-M 7FFFh AT89C5131A-M Virgin Application Application Virgin...
Page 43: Eeprom Data Memory
AT89C5130A/31A-M 10. EEPROM Data Memory 10.1 Description The 1-Kbyte on-chip EEPROM memory block is located at addresses 0000h to 03FFh of the ERAM memory space and is selected by setting control bits in the EECON register. A read in the EEPROM memory is done with a MOVX instruction. A physical write in the EEPROM memory is done in two steps: write data in the column latches and transfer of all data latches into an EEPROM memory row (programming).
Page 44: Registers
10.5 Registers Table 10-1. EECON (S:0D2h) EECON Register EEPL3 EEPL2 EEPL1 EEPL0 EEBUSY Bit Number Mnemonic Description Programming Launch command bits EEPL3-0 Write 5Xh followed by AXh to EEPL to launch the programming. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate.
Page 45: In-System Programming (Isp)
There are three methods for programming the Flash memory: • The Atmel bootloader located in FM1 is activated by the application. Low level API routines (located in FM1)will be used to program FM0. The interface used for serial downloading to FM0 is the USB.
Page 46: Boot Process
- This bit indicates if on RESET the user wants to jump to this application at address @0000h on FM0 or execute the boot loader at address @F400h on FM1. - BLJB = 0 (i.e. bootloader FM1 executed after a reset) is the default Atmel factory programming. -To read or modify this bit, the APIs are used.
Page 47: Application-Programming-Interface
Several Application Program Interface (API) calls are available for use by an application pro- gram to permit selective erasing and programming of Flash pages. All calls are made by functions. All these APIs are described in detail in the following document on the Atmel web site. – Datasheet Bootloader USB AT89C5131. 11.4 XROW Bytes The EXTRA ROW (XROW) includes 128 bytes.
Page 48: Hardware Conditions
Description Default Value Address Copy of the Device ID#3: Name and Revision 11.5 Hardware Conditions It is possible to force the controller to execute the bootloader after a Reset with hardware condi- tions. Depending on the product type (low pin count or high pin count package), there are two methods to apply the hardware conditions.
Page 49 AT89C5130A/31A-M Figure 11-4. Hardware conditions typical sequence during power-on. PSEN 11.5.2 Low Pin Count Hardware Conditions (QFN32) Low pin count products do not have PSEN signal, thus for these products, the bootloader is always executed after reset thanks to the BLJB bit. The Hardware Condition are detected at the begining of the bootloader execution from reset.
Page 50: On-Chip Expanded Ram (Eram)
12. On-chip Expanded RAM (ERAM) The AT89C5130A/31A-M provides additional Bytes of random access memory (RAM) space for increased data parameters handling and high level language usage. AT89C5130A/31A-M devices have expanded RAM in external data space; maximum size and location are described in Table 12-1. Table 12-1.
Page 51 AT89C5130A/31A-M • Instructions that use direct addressing access SFR space. For example: MOV 0A0H, # data, accesses the SFR at location 0A0h (which is P2). • Instructions that use indirect addressing access the Upper 128 bytes of data RAM. For example: MOV atR0, # data where R0 contains 0A0h, accesses the data byte at address 0A0h, rather than P2 (whose address is 0A0h).
Page 52 Number Mnemonic Description Pulse length Cleared to stretch MOVX control: the RD and the WR pulse length is 6 clock periods (default). Set to stretch MOVX control: the RD and the WR pulse length is 30 clock periods. Reserved The value read from this bit is indeterminate. Do not set this bit XRS1 ERAM Size XRS1XRS0...
Page 53: Timer 2
The Auto-reload mode configures Timer 2 as a 16-bit timer or event counter with automatic reload. If DCEN bit in T2MOD is cleared, Timer 2 behaves as in 80C52 (refer to the Atmel 8-bit microcontroller hardware description). If DCEN bit is set, Timer 2 acts as an Up/down...
Page 54: Programmable Clock Output
Figure 13-1. Auto-reload Mode Up/Down Counter (DCEN = 1) CLK PERIPH C/T2 T2CON T2CON (DOWN COUNTING RELOAD VALUE) T2EX: if DCEN = 1, 1 = UP (8-bit) (8-bit) if DCEN = 1, 0 = DOWN if DCEN = 0, up counting TOGGLE T2CON EXF2...
Page 55 AT89C5130A/31A-M It is possible to use Timer 2 as a baud rate generator and a clock generator simultaneously. For this configuration, the baud rates and clock frequencies are not independent since both func- tions use the values in the RCAP2H and RCAP2L registers. Figure 13-2.
Page 56 Table 13-1. T2CON Register T2CON - Timer 2 Control Register (C8h) EXF2 RCLK TCLK EXEN2 C/T2# CP/RL2# Number Mnemonic Description Timer 2 overflow Flag Must be cleared by software. Set by hardware on Timer 2 overflow, if RCLK = 0 and TCLK = 0. Timer 2 External Flag Set when a capture or a reload is caused by a negative transition on T2EX pin if EXEN2 = 1.
Page 57 AT89C5130A/31A-M Table 13-2. T2MOD Register T2MOD - Timer 2 Mode Control Register (C9h) T2OE DCEN Number Mnemonic Description Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate.
Page 58: Programmable Counter Array (Pca)
14. Programmable Counter Array (PCA) The PCA provides more timing capabilities with less CPU intervention than the standard timer/counters. Its advantages include reduced software overhead and improved accuracy. The PCA consists of a dedicated timer/counter which serves as the time base for an array of five compare/capture modules.
Page 59 AT89C5130A/31A-M Figure 14-1. PCA Timer/Counter To PCA modules CLK PERIPH overflow CLK PERIPH T0 OVF 16 Bit Up Counter P1.2 CMOD CIDL WDTE CPS1 CPS0 0xD9 Idle CCON CCF4 CCF3 CCF2 CCF1 CCF0 0xD8 Table 14-1. CMOD Register CMOD - PCA Counter Mode Register (D9h) CIDL WDTE CPS1...
Page 60 Reset Value = 00XX X000b Not bit addressable The CMOD register includes three additional bits associated with the PCA (See Figure 14-1 and Table 14-1). • The CIDL bit allows the PCA to stop during idle mode. • The WDTE bit enables or disables the watchdog function on module 4. •...
Page 61 AT89C5130A/31A-M Number Mnemonic Description PCA Module 1 Interrupt Flag CCF1 Must be cleared by software. Set by hardware when a match or capture occurs. PCA Module 0 Interrupt Flag CCF0 Must be cleared by software. Set by hardware when a match or capture occurs. Reset Value = 000X 0000b Not bit addressable The watchdog timer function is implemented in module 4 (See Figure 14-4).
Page 62 • The ECCF bit (CCAPMn.0 where n = 0, 1, 2, 3, or 4 depending on the module) enables the CCF flag in the CCON SFR to generate an interrupt when a match or compare occurs in the associated module. •...
Page 63 AT89C5130A/31A-M Number Mnemonic Description Pulse Width Modulation Mode PWMn Cleared to disable the CEXn pin to be used as a pulse width modulated output. Set to enable the CEXn pin to be used as a pulse width modulated output. Enable CCF Interrupt Cleared to disable compare/capture flag CCFn in the CCON register to generate an ECCFn interrupt.
Page 64 Reset Value = XXXX XXXXb Not bit addressable Table 14-6. CCAPnL Registers (n = 0-4) CCAP0L - PCA Module 0 Compare/Capture Control Register Low (0EAh) CCAP1L - PCA Module 1 Compare/Capture Control Register Low (0EBh) CCAP2L - PCA Module 2 Compare/Capture Control Register Low (0ECh) CCAP3L - PCA Module 3 Compare/Capture Control Register Low (0EDh) CCAP4L - PCA Module 4 Compare/Capture Control Register Low (0EEh) Number...
Page 65: Pca Capture Mode
AT89C5130A/31A-M 14.1 PCA Capture Mode To use one of the PCA modules in the capture mode either one or both of the CCAPM bits CAPN and CAPP for that module must be set. The external CEX input for the module (on port 1) is sampled for a transition.
Page 66: High Speed Output Mode
Figure 14-4. PCA Compare Mode and PCA Watchdog Timer CCON 0xD8 CCF4 CCF3 CCF2 CCF1 CCF0 Write to CCAPnL Reset PCA IT Write to CCAPnH CCAPnH CCAPnL Enable Match 16-bit Comparator RESET PCA Counter/Timer CCAPMn, n = 0 to 4 ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn...
Page 67: Pulse Width Modulator Mode
AT89C5130A/31A-M Figure 14-5. PCA High-speed Output Mode CCON CCF4 CCF3 CCF2 CCF1 CCF0 0xD8 Write to Reset CCAPnL PCA IT Write to CCAPnH CCAPnH CCAPnL Enable Match 16-bit Comparator CEXn PCA counter/timer CCAPMn, n = 0 to 4 ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn 0xDA to 0xDE Before enabling ECOM bit, CCAPnL and CCAPnH should be set with a non zero value, other-...
Page 68: Pca Watchdog Timer
Figure 14-6. PCA PWM Mode CCAPnH Overflow CCAPnL “0” CEXn Enable < 8-bit Comparator ≥ “1” PCA Counter/Timer CCAPMn, n = 0 to 4 ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn 0xDA to 0xDE 14.5 PCA Watchdog Timer An on-board watchdog timer is available with the PCA to improve the reliability of the system without increasing chip count.
Page 69: Serial I/O Port
AT89C5130A/31A-M 15. Serial I/O Port The serial I/O port in the AT89C5130A/31A-M is compatible with the serial I/O port in the 80C52. It provides both synchronous and asynchronous communication modes. It operates as an Uni- versal Asynchronous Receiver and Transmitter (UART) in three full-duplex modes (modes 1, 2 and 3).
Page 70: Automatic Address Recognition
Figure 15-3. UART Timings in Modes 2 and 3 Start Data Byte Ninth Stop SMOD0 = 0 SMOD0 = 1 SMOD0 = 1 15.2 Automatic Address Recognition The automatic address recognition feature is enabled when the multiprocessor communication feature is enabled (SM2 bit in SCON register is set). Implemented in hardware, automatic address recognition enhances the multiprocessor commu- nication feature by allowing the serial port to examine the address of each incoming command frame.
Page 71 AT89C5130A/31A-M Slave C:SADDR1111 0011b SADEN1111 1101b Given1111 00X1b The SADEN byte is selected so that each slave may be addressed separately. For slave A, bit 0 (the LSB) is a don’t care bit; for slaves B and C, bit 0 is a 1. To communicate with slave A only, the master must send an address where bit 0 is clear (e.g.
Page 72: Baud Rate Selection For Uart For Mode 1 And 3
SADEN - Slave Address Mask Register (B9h) Reset Value = 0000 0000b Not bit addressable SADDR - Slave Address Register (A9h) Reset Value = 0000 0000b Not bit addressable 15.3 Baud Rate Selection for UART for Mode 1 and 3 The Baud Rate Generator for transmit and receive clocks can be selected separately via the T2CON and BDRCON registers.
Page 73 AT89C5130A/31A-M 15.3.1 Baud Rate Selection Table for UART TCLK RCLK TBCK RBCK Clock Source Clock Source (T2CON) (T2CON) (BDRCON) (BDRCON) UART Tx UART Rx Timer 1 Timer 1 Timer 2 Timer 1 Timer 1 Timer 2 Timer 2 Timer 2 INT_BRG Timer 1 INT_BRG...
Page 74 Number Mnemonic Description Framing Error bit (SMOD0 = 1) Clear to reset the error state, not cleared by a valid stop bit. Set by hardware when an invalid stop bit is detected. SMOD0 must be set to enable access to the FE bit Serial port Mode bit 0 Refer to SM1 for serial port mode selection.
Page 75: Uart Registers
AT89C5130A/31A-M Example of computed value when X2 = 1, SMOD1 = 1, SPD = 1 = 16.384 MHz = 24 MHz Baud Rates Error (%) Error (%) 115200 1.23 0.16 57600 1.23 0.16 38400 1.23 0.16 28800 1.23 0.16 19200 0.63 0.16 9600...
Page 76 BRL - Baud Rate Reload Register for the internal baud rate generator, UART (9Ah) – – – – – – – – Reset Value = 0000 0000b Table 15-2. T2CON Register T2CON - Timer 2 Control Register (C8h) EXF2 RCLK TCLK EXEN2 C/T2#...
Page 77 AT89C5130A/31A-M Table 15-3. PCON Register PCON - Power Control Register (87h) SMOD1 SMOD0 Number Mnemonic Description Serial port Mode bit 1 for UART SMOD1 Set to select double baud rate in mode 1, 2 or 3. Serial port Mode bit 0 for UART SMOD0 Cleared to select SM0 bit in SCON register.
Page 78 Number Mnemonic Description Reserved The value read from this bit is indeterminate. Do not set this bit Reserved The value read from this bit is indeterminate. Do not set this bit Reserved The value read from this bit is indeterminate. Do not set this bit. Baud Rate Run Control bit Cleared to stop the internal Baud Rate Generator.
Page 79: Interrupt System
AT89C5130A/31A-M 16. Interrupt System 16.1 Overview The AT89C5130A/31A-M has a total of 11 interrupt vectors: two external interrupts (INT0 and INT1), three timer interrupts (timers 0, 1 and 2), the serial port interrupt, SPI interrupt, Keyboard interrupt, USB interrupt and the PCA global interrupt. These interrupts are shown in Figure 16-1. Figure 16-1.
Page 80: Registers
Each interrupt source can also be individually programmed to one out of four priority levels by setting or clearing a bit in the Interrupt Priority register (Table 16-3.) and in the Interrupt Priority High register (Table 16-4). Table 16-1. shows the bit values and priority levels associated with each combination.
Page 81 AT89C5130A/31A-M Number Mnemonic Description Enable All interrupt bit Cleared to disable all interrupts. Set to enable all interrupts. PCA interrupt enable bit Cleared to disable. Set to enable. Timer 2 overflow interrupt Enable bit Cleared to disable Timer 2 overflow interrupt. Set to enable Timer 2 overflow interrupt.
Page 82 Number Mnemonic Description Reserved The value read from this bit is indeterminate. Do not set this bit. PCA interrupt Priority bit PPCL Refer to PPCH for priority level. Timer 2 overflow interrupt Priority bit PT2L Refer to PT2H for priority level. Serial port Priority bit Refer to PSH for priority level.
Page 83 AT89C5130A/31A-M Number Mnemonic Description Reserved The value read from this bit is indeterminate. Do not set this bit. PCA interrupt Priority high bit. PPCH PPCL Priority Level Lowest PPCH Highest Timer 2 overflow interrupt Priority High bit PT2H PT2L Priority Level Lowest PT2H Highest...
Page 84 IEN1 - Interrupt Enable Register (B1h) EUSB ESPI ETWI Number Mnemonic Description Reserved USB Interrupt Enable bit EUSB Cleared to disable USB interrupt. Set to enable USB interrupt. Reserved Reserved Reserved SPI interrupt Enable bit ESPI Cleared to disable SPI interrupt. Set to enable SPI interrupt.
Page 85 AT89C5130A/31A-M Reset Value = X0XX X000b Not bit addressable Table 16-6. IPL1 Register IPL1 - Interrupt Priority Register (B2h) PUSBL PSPIL PTWIL PKBDL Number Mnemonic Description Reserved The value read from this bit is indeterminate. Do not set this bit. USB Interrupt Priority bit PUSBL Refer to PUSBH for priority level.
Page 86 Table 16-7. IPH1 Register IPH1 - Interrupt Priority High Register (B3h) PUSBH PSPIH PTWIH PKBH Number Mnemonic Description Reserved The value read from this bit is indeterminate. Do not set this bit. USB Interrupt Priority High bit PUSBH PUSBL Priority Level Lowest PUSBH Highest...
Page 87: Interrupt Sources And Vector Addresses
AT89C5130A/31A-M 16.3 Interrupt Sources and Vector Addresses Table 16-8. Vector Table Vector Polling Interrupt Interrupt Number Priority Source Request Address Reset 0000h INT0 0003h Timer 0 000Bh INT1 0013h Timer 1 001Bh UART RI+TI 0023h Timer 2 TF2+EXF2 002Bh CF + CCFn (n = 0-4) 0033h Keyboard KBDIT...
Page 88: Keyboard Interface
17. Keyboard Interface 17.1 Introduction The AT89C5130A/31A-M implements a keyboard interface allowing the connection of a 8 x n matrix keyboard. It is based on 8 inputs with programmable interrupt capability on both high or low level. These inputs are available as an alternate function of P1 and allow to exit from idle and power down modes.
Page 89: Registers
AT89C5130A/31A-M 17.2.2 Power Reduction Mode P1 inputs allow exit from idle and power down modes as detailed in section “Power-down Mode”. 17.3 Registers Table 17-1. KBF Register KBF - Keyboard Flag Register (9Eh) KBF7 KBF6 KBF5 KBF4 KBF3 KBF2 KBF1 KBF0 Bit Number Mnemonic...
Page 90 Table 17-2. KBE Register KBE - Keyboard Input Enable Register (9Dh) KBE7 KBE6 KBE5 KBE4 KBE3 KBE2 KBE1 KBE0 Number Mnemonic Description Keyboard line 7 Enable bit KBE7 Cleared to enable standard I/O pin. Set to enable KBF.7 bit in KBF register to generate an interrupt request. Keyboard line 6 Enable bit KBE6 Cleared to enable standard I/O pin.
Page 91 AT89C5130A/31A-M Table 17-3. KBLS Register KBLS-Keyboard Level Selector Register (9Ch) KBLS7 KBLS6 KBLS5 KBLS4 KBLS3 KBLS2 KBLS1 KBLS0 Bit Number Mnemonic Description Keyboard line 7 Level Selection bit KBLS7 Cleared to enable a low level detection on Port line 7. Set to enable a high level detection on Port line 7.
Page 92: Programmable Led
18. Programmable LED AT89C5130A/31A-M have up to 4 programmable LED current sources, configured by the regis- ter LEDCON. Table 18-1. LEDCON Register LEDCON (S:F1h) LED Control Register LED3 LED2 LED1 LED0 Bit Number Mnemonic Description Port LED3 Configuration Standard C51 Port LED3 2 mA current source when P3.7 is low 4 mA current source when P3.7 is low...
Page 93: Serial Peripheral Interface (Spi)
AT89C5130A/31A-M 19. Serial Peripheral Interface (SPI) The Serial Peripheral Interface module (SPI) allows full-duplex, synchronous, serial communica- tion between the MCU and peripheral devices, including other MCUs. 19.1 Features Features of the SPI module include the following: • Full-duplex, three-wire synchronous transfers •...
Page 94 19.2.3 SPI Serial Clock (SCK) This signal is used to synchronize the data movement both in and out the devices through their MOSI and MISO lines. It is driven by the Master for eight clock cycles which allows to exchange one byte on the serial lines.
Page 95: Functional Description
AT89C5130A/31A-M SPR2 SPR1 SPR0 Clock Rate Baud Rate Divisor (BD) Don’t Use No BRG 19.3 Functional Description Figure 19-2 shows a detailed structure of the SPI module. Figure 19-2. SPI Module Block Diagram Internal Bus SPDAT Shift Register FCLK PERIPH Clock Receive Data Register Divider...
Page 96 When the Master device transmits data to the Slave device via the MOSI line, the Slave device responds by sending data to the Master device via the MISO line. This implies full-duplex trans- mission with both data out and data in synchronized with the same clock (Figure 19-3). Figure 19-3.
Page 97 AT89C5130A/31A-M output data are shifted (Figure 19-4 and Figure 19-5). The clock phase and polarity should be identical for the Master SPI device and the communicating Slave device. Figure 19-4. Data Transmission Format (CPHA = 0) SCK cycle number SPEN (internal) SCK (CPOL = 0) SCK (CPOL = 1) MOSI (from Master)
Page 98 19.3.3 Error Conditions The following flags in the SPSTA signal SPI error conditions: 19.3.3.1 Mode Fault (MODF) Mode Fault error in Master mode SPI indicates that the level on the Slave Select (SS) pin is inconsistent with the actual mode of the device. MODF is set to warn that there may have a multi-master conflict for system control.
Page 99 AT89C5130A/31A-M Mode Fault flag, MODF: This bit becomes set to indicate that the level on the SS is inconsistent with the mode of the SPI. MODF with SSDIS reset, generates receiver/error CPU interrupt requests. Figure 19-7 gives a logical view of the above statements. Figure 19-7.
Page 100 Number Bit Mnemonic Description Clock Phase CPHA Cleared to have the data sampled when the SCK leaves the idle state (see CPOL). Set to have the data sampled when the SCK returns to idle state (see CPOL). SPR2 SPR1 SPR0 Serial Peripheral Rate SPR1 000Reserved 00 1F...
Page 101 AT89C5130A/31A-M Bit Number Mnemonic Description Mode Fault Cleared by hardware to indicate that the SS pin is at appropriate logic level, or has been MODF approved by a clearing sequence. Set by hardware to indicate that the SS pin is at inappropriate logic level. Reserved The value read from this bit is indeterminate.
Page 102: Two Wire Interface (Twi)
20. Two Wire Interface ( This section describes the 2-wire interface. The 2-wire bus is a bi-directional 2-wire serial com- munication standard. It is designed primarily for simple but efficient integrated circuit (IC) control. The system is comprised of two lines, SCL (Serial Clock) and SDA (Serial Data) that carry infor- mation between the ICs connected to them.
Page 103 AT89C5130A/31A-M Figure 20-2. Block Diagram Address Register SSADR Comparator Input Filter Output Stage SSDAT Shift Register Arbitration & Input Sink Logic Filter Timing & Control CLK PERIPH logic Interrupt Output Serial clock Stage generator Timer 1 overflow Control Register SSCON Status Status Decoder...
Page 104: Description
20.1 Description The CPU interfaces to the 2-wire logic via the following four 8-bit special function registers: the Synchronous Serial Control register (SSCON; Table 20-10), the Synchronous Serial Data regis- ter (SSDAT; Table 20-11), the Synchronous Serial Control and Status register (SSCS; Table 20- 12) and the Synchronous Serial Address register (SSADR Table...
Page 105 AT89C5130A/31A-M : Read bit (high level at SDA) : Write bit (low level at SDA) Acknowledge bit (low level at SDA) A: Not acknowledge bit (high level at SDA) Data: 8-bit data byte : STOP condition In Figure 20-4 to Figure 20-7, circles are used to indicate when the serial interrupt flag is set. The numbers in the circles show the status code held in SSCS.
Page 106 address and the data direction bit (SLA+R). The serial interrupt flag SI must then be cleared before the serial transfer can continue. When the slave address and the direction bit have been transmitted and an acknowledgement bit has been received, the serial interrupt flag is set again and a number of status code in SSCS are possible.
Page 107: Notes
AT89C5130A/31A-M 20.1.4 Slave Transmitter Mode In the slave transmitter mode, a number of data bytes are transmitted to a master receiver (Figure 20-7). Data transfer is initialized as in the slave receiver mode. When SSADR and SSCON have been initialized, the TWI module waits until it is addressed by its own slave address followed by the data direction bit which must be at logic 1 (R) for TWI to operate in the slave transmitter mode.
Page 108 Bit Frequency ( kHz) = 12 MHz = 16 MHz divided by OSCA OSCA OSCA Unused 133.3 266.6 Timer 1 in mode 2 can be used as TWI baudrate generator with the following formula: 0.5 <. < 62.5 0.67 <. < 83 96.(256-”Timer1 reload value”) AT89C5130A/31A-M 4337K–USB–04/08...
Page 109 AT89C5130A/31A-M Figure 20-4. Format and State in the Master Transmitter Mode Successfull Data transmission to a slave receiver Next transfer started with a repeated start condition Not acknowledge received after the slave address Not acknowledge received after a data byte Arbitration lost in slave Other master Other master...
Page 110 Table 20-5. Status in Master Transmitter Mode Application software response Status Status of the Two- To SSCON Code wire Bus and Two- SSSTA wire Hardware To/From SSDAT SSSTA SSSTO SSAA Next Action Taken by Two-wire Hardware A START condition has Write SLA+W SLA+W will be transmitted.
Page 111 AT89C5130A/31A-M Figure 20-5. Format and State in the Master Receiver Mode Successfull Data transmission Data to a slave receiver Next transfer started with a repeated start condition Not acknowledge received after the slave address Arbitration lost in slave Other master Other master A or A address or acknowledge bit...
Page 112 Table 20-6. Status in Master Receiver Mode Application software response Status Status of the Two- To SSCON Code wire Bus and Two- SSSTA wire Hardware To/From SSDAT SSSTA SSSTO SSAA Next Action Taken by Two-wire Hardware A START condition has Write SLA+R SLA+R will be transmitted.
Page 113 AT89C5130A/31A-M Figure 20-6. Format and State in the Slave Receiver Mode Reception of the own P or S Data Data slave address and one or more data bytes. All are acknowledged. Last data byte received P or S is not acknowledged. Arbitration lost as master and addressed as slave Reception of the general call...
Page 114 Table 20-7. Status in Slave Receiver Mode Application Software Response To/from SSDAT To SSCON Status Code Status of the 2-wire bus and (SSCS) 2-wire hardware Next Action Taken By 2-wire Software Data byte will be received and NOT ACK will be No SSDAT action or Own SLA+W has been returned...
Page 115 AT89C5130A/31A-M Table 20-7. Status in Slave Receiver Mode (Continued) Application Software Response To/from SSDAT To SSCON Status Code Status of the 2-wire bus and (SSCS) 2-wire hardware Next Action Taken By 2-wire Software Switched to the not addressed slave mode; no recognition of own SLA or GCA Read data byte or Switched to the not addressed slave mode;...
Page 116 Figure 20-7. Format and State in the Slave Transmitter Mode Reception of the P or S Data Data own slave address and one or more data bytes Arbitration lost as master and addressed as slave Last data byte transmitted. All 1’s P or S Switched to not addressed slave (AA=0)
Page 117 AT89C5130A/31A-M Table 20-8. Status in Slave Transmitter Mode (Continued) Application Software Response To/from SSDAT To SSCON Status Code Status of the 2-wire bus and (SSCS) 2-wire hardware Next Action Taken By 2-wire Software Switched to the not addressed slave mode; no recognition of own SLA or GCA No SSDAT action or Switched to the not addressed slave mode;...
Page 118: Registers
20.3 Registers Table 20-10. SSCON Register SSCON - Synchronous Serial Control Register (93h) SSIE Bit Number Mnemonic Description Control Rate bit 2 See . Synchronous Serial Interface Enable bit SSIE Clear to disable SSLC. Set to enable SSLC. Start flag Set to send a START condition on the bus.
Page 119 AT89C5130A/31A-M Bit Number Mnemonic Description Address bit 1 or Data bit 1. Address bit 0 (R/W) or Data bit 0. Table 20-12. SSCS (094h) Read - Synchronous Serial Control and Status Register Bit Number Mnemonic Description Always zero Always zero Always zero Status Code bit 0 See Table 20-5 to Table 20-9...
Page 120: Usb Controller
21. USB Controller 21.1 Description The USB device controller provides the hardware that the AT89C5131 needs to interface a USB link to a data flow stored in a double port memory (DPRAM). The USB controller requires a 48 MHz ±0.25% reference clock, which is the output of the AT89C5131 PLL (see Section “PLL”, page 15) divided by a clock prescaler.
Page 121 AT89C5130A/31A-M • Address checking. • Clock generation (via DPLL). Figure 21-2. SIE Block Diagram End of Packet Detection SYNC Detection Start of Packet Detection PID Decoder NRZI ‘NRZ Bit Un-stuffing Packet Bit Counter DataOut Address Decoder Serial to P a r a l l e l Clock SysClk Recovery...
Page 122: Configuration
Figure 21-3. UFI Block Diagram Asynchronous Information CSREG 0 to 7 DPLL Transfer Microcontroller Transfer Interface Control Endpoint 6 Registers Endpoint 5 Bank Endpoint 4 Endpoint 3 Endpoint 2 Endpoint 1 DPR Control DPR Control Up to 48 MHz Endpoint 0 USB Side mP side UC_sysclk...
Page 123 AT89C5130A/31A-M • Set configuration The CONFG bit in the USBCON register has to be set after a SET_CONFIGURATION request with a non-zero value. Otherwise, this bit has to be cleared. 21.2.2 Endpoint Configuration • Selection of an Endpoint The endpoint register access is performed using the UEPNUM register. The registers –...
Page 124: Read/Write Data Fifo
The Endpoint 0 is the Default Control Endpoint and will always be configured in Control type. • Endpoint direction configuration For Bulk, Interrupt and Isochronous endpoints, the direction is defined with the EPDIR bit of the UEPCONX register with the following values: –...
Page 125: Bulk/Interrupt Transactions
AT89C5130A/31A-M Figure 21-6. Endpoint FIFO Configuration UEPSTA0 UEPCON0 UEPDAT0 Endpoint 0 SFR registers UBYCTH0 UBYCTL0 UEPSTAX UEPCONX UEPDATX UBYCTHX UBYCTLX UEPSTA6 UEPCON6 UEPDAT6 Endpoint 6 UBYCTH6 UBYCTL6 UEPNUM 21.3.2 Read Data FIFO The read access for each OUT endpoint is performed using the UEPDATX register. After a new valid packet has been received on an Endpoint, the data are stored into the FIFO and the byte counter of the endpoint is updated (UBYCTLX and UBYCTHX registers).
Page 126 21.4.1 Bulk/Interrupt OUT Transactions in Standard Mode Figure 21-7. Bulk/Interrupt OUT transactions in Standard Mode HOST DATA0 (n bytes) RXOUTB0 Endpoint FIFO read byte 1 DATA1 Endpoint FIFO read byte 2 Endpoint FIFO read byte n DATA1 Clear RXOUTB0 DATA1 RXOUTB0 Endpoint FIFO read byte 1 An endpoint will be first enabled and configured before being able to receive Bulk or Interrupt...
Page 127 AT89C5130A/31A-M 21.4.2 Bulk/Interrupt OUT Transactions in Ping-pong Mode Figure 21-8. Bulk/Interrupt OUT Transactions in Ping-pong Mode HOST DATA0 (n Bytes) RXOUTB0 Endpoint FIFO Bank 0 - Read Byte 1 Endpoint FIFO Bank 0 - Read Byte 2 DATA1 (m Bytes) Endpoint FIFO Bank 0 - Read Byte n Clear RXOUTB0 RXOUTB1...
Page 128 A NAK handshake is sent by the USB controller only if the banks 0 and 1 has not been released by the firmware. If the Host sends more bytes than supported by the endpoint FIFO, the overflow data won’t be stored, but the USB controller will consider that the packet is valid if the CRC is correct.
Page 129 AT89C5130A/31A-M 21.4.4 Bulk/Interrupt IN Transactions in Ping-pong Mode Figure 21-10. Bulk/Interrupt IN Transactions in Ping-pong Mode HOST Endpoint FIFO Bank 0 - Write Byte 1 Endpoint FIFO Bank 0 - Write Byte 2 NACK Endpoint FIFO Bank 0 - Write Byte n Set TXRDY Endpoint FIFO Bank 1 - Write Byte 1 DATA0 (n Bytes)
Page 130: Control Transactions
The firmware will never write more bytes than supported by the endpoint FIFO. 21.5 Control Transactions 21.5.1 Setup Stage The DIR bit in the UEPSTAX register will be at 0. Receiving Setup packets is the same as receiving Bulk Out packets, except that the RXSETUP bit in the UEPSTAX register is set by the USB controller instead of the RXOUTB0 bit to indicate that an Out packet with a Setup PID has been received on the Control endpoint.
Page 131: Isochronous Transactions
AT89C5130A/31A-M 21.6 Isochronous Transactions 21.6.1 Isochronous OUT Transactions in Standard Mode An endpoint will be first enabled and configured before being able to receive Isochronous packets. When a OUT packet is received on an endpoint, the RXOUTB0 bit is set by the USB controller. This triggers an interrupt if enabled.
Page 132: Miscellaneous
The firmware has to clear one of these two bits after having read all the data FIFO to allow a new packet to be stored in the corresponding bank. If the Host sends more bytes than supported by the endpoint FIFO, the overflow data won’t be stored, but the USB controller will consider that the packet is valid if the CRC is correct.
Page 133: Suspend/Resume Management
AT89C5130A/31A-M 21.7.2 STALL Handshake This function is only available for Control, Bulk, and Interrupt endpoints. The firmware has to set the STALLRQ bit in the UEPSTAX register to send a STALL handshake at the next request of the Host on the endpoint selected with the UEPNUM register. The RXSETUP, TXRDY, TXCMPL, RXOUTB0 and RXOUTB1 bits must be first reset to 0.
Page 134 The stop of the 48 MHz clock from the PLL should be done in the following order: 1. Clear suspend interrupt bit in USBINT (required to allow the USB pads to enter power down mode). 2. Enable USB resume interrupt. 3.
Page 135: Detach Simulation
AT89C5130A/31A-M When the USB controller receives the SET_FEATURE request: DEVICE_REMOTE_WAKEUP, the firmware will set to 1 the RMWUPE bit in the USBCON register to enable this functionality. RMWUPE value will be 0 in the other cases. If the device is in SUSPEND mode, the USB controller can send an upstream resume by clear- ing first the SPINT bit in the USBINT register and by setting then to 1 the SDRMWUP bit in the USBCON register.
Page 136: Usb Interrupt System
Figure 21-13. Example of V Connection 1.5 kW AT89C5131 USB-B Connector Figure 21-14. Disconnect Timing (min) > = 2,5 ms Disconnect Device Detected Disconnected 21.10 USB Interrupt System 21.10.1 Interrupt System Priorities Figure 21-15. USB Interrupt Control System Controller EUSB IPH/L IE1.6 IE0.7...
Page 137 AT89C5130A/31A-M 21.10.2 USB Interrupt Control System As shown in Figure 21-16, many events can produce a USB interrupt: • TXCMPL: Transmitted In Data (see Table 21-9 on page 144). This bit is set by hardware when the Host accept a In packet. •...
Page 138 Figure 21-16. USB Interrupt Control Block Diagram Endpoint X (X = 0..6) TXCMP UEPSTAX.0 RXOUTB0 UEPSTAX.1 RXOUTB1 EPXINT UEPINT.X UEPSTAX.6 EPXIE RXSETUP UEPSTAX.2 UEPIEN.X STLCRC UEPSTAX.3 WUPCPU EUSB USBINT.5 IE1.6 EWUPCPU USBIEN.5 EORINT USBINT.4 EEORINT USBIEN.4 SOFINT USBINT.3 ESOFINT USBIEN.3 SPINT USBINT.0 ESPINT...
Page 139: Usb Registers
AT89C5130A/31A-M 21.11 USB Registers Table 21-3. USBCON Register USBCON (S:BCh) USB Global Control Register USBE SUSPCLK SDRMWUP DETACH UPRSM RMWUPE CONFG FADDEN Bit Number Bit Mnemonic Description USB Enable Set this bit to enable the USB controller. USBE Clear this bit to disable and reset the USB controller, to disable the USB transceiver an to disable the USB controller clock inputs.
Page 140 Table 21-4. USBINT Register USBINT (S:BDh) USB Global Interrupt Register WUPCPU EORINT SOFINT SPINT Bit Number Mnemonic Description Reserved The value read from these bits is always 0. Do not set these bits. Wake Up CPU Interrupt This bit is set by hardware when the USB controller is in SUSPEND state and is re- activated by a non-idle signal FROM USB line (not by an upstream resume).
Page 141 AT89C5130A/31A-M Table 21-5. USBIEN Register USBIEN (S:BEh) USB Global Interrupt Enable Register EWUPCPU EEORINT ESOFINT ESPINT Bit Number Bit Mnemonic Description Reserved The value read from these bits is always 0. Do not set these bits. Enable Wake Up CPU Interrupt Set this bit to enable Wake Up CPU Interrupt.
Page 142 Table 21-6. USBADDR Register USBADDR (S:C6h) USB Address Register UADD6 UADD5 UADD4 UADD3 UADD2 UADD1 UADD0 Bit Number Mnemonic Description Function Enable Set this bit to enable the address filtering function. Cleared this bit to disable the function. USB Address This field contains the default address (0) after power-up or USB bus reset.
Page 143 AT89C5130A/31A-M Table 21-8. UEPCONX Register UEPCONX (S:D4h) USB Endpoint X Control Register EPEN DTGL EPDIR EPTYPE1 EPTYPE0 Bit Number Bit Mnemonic Description Endpoint Enable Set this bit to enable the endpoint according to the device configuration. Endpoint 0 will EPEN always be enabled after a hardware or USB bus reset and participate in the device configuration.
Page 144 Table 21-9. UEPSTAX (S:CEh) USB Endpoint X Status Register RXOUTB1 STALLRQ TXRDY STL/CRC RXSETUP RXOUTB0 TXCMP Bit Number Mnemonic Description Control Endpoint Direction This bit is used only if the endpoint is configured in the control type (seeSection “UEPCONX Register UEPCONX (S:D4h) USB Endpoint X Control Register”).
Page 145 AT89C5130A/31A-M Table 21-10. UEPDATX Register UEPDATX (S:CFh) USB FIFO Data Endpoint X (X = EPNUM set in UEPNUM Register UEPNUM FDAT7 FDAT6 FDAT5 FDAT4 FDAT3 FDAT2 FDAT1 FDAT0 Bit Number Mnemonic Description Endpoint X FIFO data FDAT 7 - 0 [7:0] Data byte to be written to FIFO or data byte to be read from the FIFO, for the Endpoint X (see EPNUM).
Page 146 Table 21-12. UBYCTHX Register UBYCTHX (S:E3h) USB Byte Count High Register X (X = EPNUM set in UEPNUM Register UEP- BYCT9 BYCT8 Bit Number Bit Mnemonic Description Reserved The value read from these bits is always 0. Do not set these bits. Byte Count MSB Most Significant Byte of the byte count of a received data packet.
Page 147 AT89C5130A/31A-M Table 21-13. UEPRST Register UEPRST (S:D5h) USB Endpoint FIFO Reset Register EP6RST EP5RST EP4RST EP3RST EP2RST EP1RST EP0RST Bit Number Mnemonic Description Reserved The value read from this bit is always 0. Do not set this bit. Endpoint 6 FIFO Reset Set this bit and reset the endpoint FIFO prior to any other operation, upon hardware reset EP6RST or when an USB bus reset has been received.
Page 148 Table 21-14. UEPINT Register UEPINT (S:F8h read-only) USB Endpoint Interrupt Register EP6INT EP5INT EP4INT EP3INT EP2INT EP1INT EP0INT Bit Number Mnemonic Description Reserved The value read from this bit is always 0. Do not set this bit. Endpoint 6 Interrupt This bit is set by hardware when an endpoint interrupt source has been detected on the endpoint 6.
Page 149 AT89C5130A/31A-M Table 21-15. UEPIEN Register UEPIEN (S:C2h) USB Endpoint Interrupt Enable Register EP6INTE EP5INTE EP4INTE EP3INTE EP2INTE EP1INTE EP0INTE Bit Number Mnemonic Description Reserved The value read from this bit is always 0. Do not set this bit. Endpoint 6 Interrupt Enable EP6INTE Set this bit to enable the interrupts for this endpoint.
Page 150 Table 21-16. UFNUMH Register UFNUMH (S:BBh, read-only) USB Frame Number High Register CRCOK CRCERR FNUM10 FNUM9 FNUM8 Number Bit Mnemonic Description Frame Number CRC OK This bit is set by hardware when a new Frame Number in Start of Frame Packet is CRCOK received without CRC error.
Page 151: Reset
AT89C5130A/31A-M 22. Reset 22.1 Introduction The reset sources are: Power Management, Hardware Watchdog, PCA Watchdog and Reset input. Figure 22-1. Reset schematic Power Monitor Hardware Internal Reset Watchdog Watchdog 22.2 Reset Input The Reset input can be used to force a reset pulse longer than the internal reset controlled by the Power Monitor.
Page 152 Figure 22-3. Recommended Reset Output Schematic AT89C5131A-M To other on-board circuitry AT89C5130A/31A-M 4337K–USB–04/08...
Page 153: Power Monitor
AT89C5130A/31A-M 23. Power Monitor The POR/PFD function monitors the internal power-supply of the CPU core memories and the peripherals, and if needed, suspends their activity when the internal power supply falls below a safety threshold. This is achieved by applying an internal reset to them. By generating the Reset the Power Monitor insures a correct start up when AT89C5131 is pow- ered up.
Page 154 Figure 23-2. Power Fail Detect Reset When the power is applied, the Power Monitor immediately asserts a reset. Once the internal supply after the voltage regulator reach a safety level, the power monitor then looks at the XTAL clock input. The internal reset will remain asserted until the Xtal1 levels are above and below VIH and VIL.
Page 155: Power Management
AT89C5130A/31A-M 24. Power Management 24.1 Idle Mode An instruction that sets PCON.0 indicates that it is the last instruction to be executed before going into the Idle mode. In the Idle mode, the internal clock signal is gated off to the CPU, but not to the interrupt, Timer, and Serial Port functions.
Page 156 Figure 24-1. Power-down Exit Waveform INT0 INT1 XTAL Active Phase Power-down Phase Oscillator restart Phase Active Phase Exit from power-down by reset redefines all the SFRs, exit from power-down by external inter- rupt does no affect the SFRs. Exit from power-down by either reset or external interrupt does not affect the internal RAM content.
Page 157: Registers
AT89C5130A/31A-M 24.3 Registers Table 24-2. PCON Register PCON (S:87h) Power Control Register SMOD1 SMOD0 Bit Number Mnemonic Description Serial Port Mode bit 1 SMOD1 Set to select double baud rate in mode 1, 2 or 3. Serial Port Mode bit 0 SMOD0 Set to select FE bit in SCON register.
Page 158: Hardware Watchdog Timer
25. Hardware Watchdog Timer The WDT is intended as a recovery method in situations where the CPU may be subjected to software upset. The WDT consists of a 14-bit counter and the WatchDog Timer ReSeT (WDTRST) SFR. The WDT is by default disabled from exiting reset. To enable the WDT, user must write 01EH and 0E1H in sequence to the WDTRST, SFR location 0A6H.
Page 159: Wdt During Power-Down And Idle
AT89C5130A/31A-M Table 25-2. WDTPRG Register WDTPRG - Watchdog Timer Out Register (0A7h) Number Mnemonic Description Reserved The value read from this bit is undetermined. Do not try to set this bit. WDT Time-out select bit 2 WDT Time-out select bit 1 WDT Time-out select bit 0 S2 S1 S0 Selected Time-out 16384x2^(214 - 1) machine cycles, 16.3 ms at FOSC = 12 MHz...
Page 160: Reduced Emi Mode
26. Reduced EMI Mode The ALE signal is used to demultiplex address and data buses on port 0 when used with exter- nal program or data memory. Nevertheless, during internal code execution, ALE signal is still generated. In order to reduce EMI, ALE signal can be disabled by setting AO bit. The AO bit is located in AUXR register at bit location 0.
Page 161: Electrical Characteristics
AT89C5130A/31A-M 27. Electrical Characteristics 27.1 Absolute Maximum Ratings Note: Stresses at or above those listed under “Absolute Ambient Temperature Under Bias: Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional I = industrial ............-40°C to 85°C operation of the device at these or any other condi- Storage Temperature ........
Page 162 Notes: 1. Operating I is measured with all output pins disconnected; XTAL1 driven with T = 5 ns (see Figure 27-4.), V CLCH CHCL + 0.5V, - 0.5V; XTAL2 N.C.; EA = RST = Port 0 = V would be slightly higher if a crystal oscillator used (see Figure 27-1.).
Page 163: Usb Dc Parameters
AT89C5130A/31A-M Figure 27-3. I Test Condition, Power-down Mode (NC) XTAL2 XTAL1 All other pins are disconnected. Figure 27-4. Clock Signal Waveform for I Tests in Active and Idle Modes -0.5V 0.7V 0.2V -0.1 0.45V CLCH CHCL = 5ns. CLCH CHCL 27.2.1 LED’s Table 27-1.
Page 164: Ac Parameters
Symbol Parameter Unit USB Reference Voltage Input High Voltage for D+ and D- (Driven) Input High Voltage for D+ and D- (Floating) Input Low Voltage for D+ and D- Output High Voltage for D+ and D- Output Low Voltage for D+ and D- 27.4 AC Parameters 27.4.1...
Page 165 AT89C5130A/31A-M 27.4.2 External Program Memory Characteristics Table 27-2. Symbol Description Symbol Parameter Oscillator Clock Period ALE Pulse Width LHLL Address Valid to ALE AVLL Address Hold after ALE LLAX ALE to Valid Instruction In LLIV ALE to PSEN LLPL PSEN Pulse Width PLPH PSEN to Valid Instruction In PLIV...
Page 166 Table 27-4. AC Parameters for a Variable Clock Standard Symbol Type Clock X2 Clock X Parameter Units 2 T - x T - x LHLL T - x 0.5 T - x AVLL T - x 0.5 T - x LLAX 4 T - x 2 T - x...
Page 167 AT89C5130A/31A-M 27.4.4 External Data Memory Characteristics Table 27-5. Symbol Description Symbol Parameter RD Pulse Width RLRH WR Pulse Width WLWH RD to Valid Data In RLDV Data Hold After RD RHDX Data Float After RD RHDZ ALE to Valid Data In LLDV Address to Valid Data In AVDV...
Page 168 Table 27-7. AC Parameters for a Variable Clock Standard Symbol Type Clock X2 Clock X Parameter Units 6 T - x 3 T - x RLRH 6 T - x 3 T - x WLWH 5 T - x 2.5 T - x RLDV RHDX 2 T - x...
Page 169 AT89C5130A/31A-M 27.4.6 External Data Memory Read Cycle WHLH LLDV PSEN LLWL RLRH RHDZ AVDV LLAX RHDX PORT 0 A0-A7 DATA IN RLAZ AVWL ADDRESS PORT 2 ADDRESS A8-A15 OR SFR P2 OR SFR-P2 27.4.7 Serial Port Timing - Shift Register Mode Table 27-8.
Page 170 27.4.8 Shift Register Timing Waveform INSTRUCTION XLXL CLOCK XHQX QVXH OUTPUT DATA SET TI XHDX WRITE to SBUF XHDV INPUT DATA VALID VALID VALID VALID VALID VALID VALID VALID SET RI CLEAR RI 27.4.9 External Clock Drive Characteristics (XTAL1) Table 27-11. AC Parameters Symbol Parameter Units...
Page 171 AT89C5130A/31A-M 27.4.13 Clock Waveforms Valid in normal clock mode. In X2 mode XTAL2 must be changed to XTAL2/2. STATE4 STATE5 STATE6 STATE1 STATE2 STATE3 STATE4 STATE5 INTERNAL CLOCK XTAL2 THESE SIGNALS ARE NOT ACTIVATED DURING THE EXECUTION OF A MOVX INSTRUCTION EXTERNAL PROGRAM MEMORY FETCH PSEN DATA...
Page 172 27.4.14 Flash EEPROM Memory and Data EEPROM Memory Table 27-12. Timing Symbol Definitions Signals Conditions S (Hardware PSEN, EA Condition) Valid FBUSY Flag No Longer Valid Table 27-13. Memory AC Timing Vcc = 3.3V ± 10%, T = -40 to +85°C Symbol Parameter Unit...
Page 173: Usb Ac Parameters
AT89C5130A/31A-M 27.5 USB AC Parameters Rise Time Fall Time Hmin Lmax Differential Data Lines Table 27-14. USB AC Parameters Symbol Parameter Unit Test Conditions Rise Time Fall Time Full-speed Data Rate 11.9700 12.0300 Mb/s FDRATE Crossover Voltage Source Jitter Total to Next -3.5 Transaction Source Jitter Total for Paired...
Page 174 = 2.7 to 5.5 V, T = -40 to +85°C Symbol Parameter Unit Slave Mode Clock Period CHCH Clock High Time CHCX Clock Low Time CLCX SS Low to Clock edge SLCH SLCL Input Data Valid to Clock Edge IVCL IVCH Input Data Hold after Clock Edge CLIX...
Page 175 AT89C5130A/31A-M 27.6.0.3 Waveforms Figure 27-7. SPI Slave Waveforms (CPHA= 0) (input) CLSH SLCH CHCH SHSL SLCL CHSH CLCH (CPOL= 0) (input) CHCX CLCX CHCL (CPOL= 1) (input) CLOX CLOV SLOV SHOX CHOX CHOV MISO SLAVE MSB OUT BIT 6 SLAVE LSB OUT (output) CHIX IVCH...
Page 176 Figure 27-9. SPI Master Waveforms (SSCPHA= 0) (output) CHCH CLCH (CPOL= 0) (output) CHCX CLCX CHCL (CPOL= 1) (output) IVCH CHIX IVCL CLIX MOSI MSB IN BIT 6 LSB IN (input) CLOX CLOV CHOV CHOX MISO Port Data MSB OUT BIT 6 LSB OUT Port Data...
Page 177: Ordering Information
Pack Tray & Dry AT89C5131A-PUTUM 2.7 to 5.5V Industrial & Green QFN32 Pack AT89C5131A-S3SUM 2.7 to 5.5V Industrial & Green PLCC52 Stick Notes: 1. Optional Packing and Package options (please consult Atmel sales representative) -Tape and Reel -Die form 4337K–USB–04/08...
Page 178: Packaging Information
29. Packaging Information 29.1 64-lead VQFP AT89C5130A/31A-M 4337K–USB–04/08...
Page 179 AT89C5130A/31A-M STANDARD NOTES FOR PQFP/ VQFP / TQFP / DQFP 1/ CONTROLLING DIMENSIONS : INCHES 2/ ALL DIMENSIONING AND TOLERANCING CONFORM TO ANSI Y 14.5M - 1982. 3/ "D1 AND E1" DIMENSIONS DO NOT INCLUDE MOLD PROTUSIONS. MOLD PROTUSIONS SHALL NOT EXCEED 0.25 mm (0.010 INCH). THE TOP PACKAGE BODY SIZE MAY BE SMALLER THAN THE BOTTOM PACKAGE BODY SIZE BY AS MUCH AS 0.15 mm.
Page 180: 52-Lead Plcc
29.2 52-lead PLCC STANDARD NOTES FOR PLCC 1/ CONTROLLING DIMENSIONS : INCHES 2/ DIMENSIONING AND TOLERANCING PER ANSI Y 14.5M - 1982. 3/ "D" AND "E1" DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTUSIONS. MOLD FLASH OR PROTUSIONS SHALL NOT EXCEED 0.20 mm (.008 INCH) PER SIDE.
Page 181: 32-Lead Qfn
AT89C5130A/31A-M 29.3 32-lead QFN 4337K–USB–04/08...
Page 182 AT89C5130A/31A-M 4337K–USB–04/08...
Page 183: Datasheet Revision History
AT89C5130A/31A-M 30. Datasheet Revision History 30.1 Changes from 4337F to 4337G 1. Added warning regarding hardware conditions on startup, see page 30.2 Changes from 4337G to 4337H 1. Hardware Conditions section Page 46 changed to recommend the use of 1K pull-up between PSEN and GND in ISP mode.
Page 184: Table Of Contents
Table of Contents Description ....................2 Block Diagram ..................3 Pinout Description ................... 4 Pinout ........................4 Signals .......................6 Typical Application ................12 Recommended External components .............12 PCB Recommandations ..................13 Clock Controller ..................14 Introduction ......................14 Oscillator ......................14 PLL ........................15 Registers ......................17 SFR Mapping ..................
Page 185 AT89C5130A/31A-M 10.3 Programming ....................43 10.4 Read Data .......................43 10.5 Registers ......................44 11 In-System Programming (ISP) .............. 45 11.1 Flash Programming and Erasure ..............45 11.2 Boot Process ....................46 11.3 Application-Programming-Interface ..............47 11.4 XROW Bytes ....................47 11.5 Hardware Conditions ..................48 12 On-chip Expanded RAM (ERAM) ............50 13 Timer 2 ....................
Page 186 19 Serial Peripheral Interface (SPI) ............93 19.1 Features ......................93 19.2 Signal Description ....................93 19.3 Functional Description ..................95 20 Two Wire Interface (TWI) ..............102 20.1 Description .....................104 20.2 Notes ......................107 20.3 Registers .......................118 21 USB Controller ..................120 21.1 Description .....................120 21.2 Configuration ....................122...
Page 187 AT89C5130A/31A-M 27 Electrical Characteristics ..............161 27.1 Absolute Maximum Ratings ................161 27.2 DC Parameters ....................161 27.3 USB DC Parameters ..................163 27.4 AC Parameters ....................164 27.5 USB AC Parameters ..................173 27.6 SPI Interface AC Parameters ................173 28 Ordering Information ................177 29 Packaging Information ................

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