Siemens Simatic S7 Series System Manual page 594

Technical specifications
A.2 S7-200 SMART CPUs
Technical data
Signal board expansion
High-speed counters
Pulse outputs
2
Pulse catch inputs
Cyclic interrupts
Edge interrupts
Memory card
Real time clock accuracy
Real time clock retention time
You can configure areas of V memory, M memory, C memory (current values) and portions of T memory (current values
1
on retentive timers) to be retentive, up to the specified maximum amount.
The specified maximum pulse frequency is possible only for CPU models with transistor outputs. Pulse output operation
2
is not recommended for CPU models with relay outputs.
Table A- 51 Performance
Type of instruction
Boolean
Move Word
Real math
Table A- 52 User program elements supported
Element
POUs Type/ quan-
tity
Nesting
depth
Accumulators Quantity
Timers Type/ quan-
tity
Counters Quantity
594
Description
CPU ST60, CPU SR60
1 max.
4 total
4 at 200 KHz single phase
•
2 at 100 KHz A/B phase
•
3 at 100 KHz
14
2 at 1 ms resolution
4 rising and 4 falling (6 and 6 with option-
al signal board)
microSDHC card (optional)
120 seconds/month
7 days typ./6 days min. at 25°C
Execution speed
150 ns instruction
1.2 μs/instruction
3.6 μs/instruction
Description
Main program: 1
Subroutines: 128 (0 to 127)
Interrupt routines: 128 (0 to 127)
From main program: 8 subroutine levels
From interrupt routine: 4 subroutine levels
4
Non-retentive (TON, TOF): 192
Retentive (TONR): 64
256
CPU CR60 AC/DC/Relay
--
4 total
4 at 100 KHz single phase
•
2 at 50 KHz A/B phase
•
--
14
2 at 1 ms resolution
4 rising and 4 falling
microSDHC card (optional)
--
--
System Manual, 09/2015, A5E03822230-AC
S7-200 SMART