Input Signal Error Detection Extended/Input Signal Error Detection/Warning Output Settings (Buffer Memory Address 47: Un\G47) - Mitsubishi MELSEC Q Series User Manual

Channel isolated high resolution analog-digital converter module / channel isolated high resolution analog-digital converter module (with signal conditioning function)
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3
SPECIFICATIONS
3.4.12 Input signal error detection extended/input signal error detection/warning output
settings (buffer memory address 47: Un\G47)
3 - 59
(1)
This area is used to set whether the input signal error detection, process alarm,
or rate alarm will be enabled or disabled for each channel.
If the warning of input signal error detection is enabled, the input signal error
detection can be performed by setting the same value of upper and lower limit or
different value of upper and lower limit.
(2)
To make the input signal error detection extended/input signal error
detection/warning output settings valid, the operating condition setting request
(Y9) must be turned ON/OFF. (Refer to Section 3.3.2.)
(3)
All channels for the input signal error detection and alarm settings set to disable,
and all channels for the input signal error detection extended setting are set to
Same upper limit value/lower limit value.
b15 b14 b13 b12 b11
CH4 CH3 CH2 CH1
Input signal error
detection extended
0: Same upper limit value/
lower limit value,
1: Different upper limit value/
lower limit value.
For Q62AD-DGH, information of b2, b3, b6, b7, b10, b14 and b15 is fixed at 0.
[Setting example of Q64AD-GH]
When performing the following settings, store 49FE
memory address 47 (Un\G47).
• The channel 1 specified for the process alarm setting is set to 0 (enabled).
• The channel 2 and 3 specified for input signal error detection are set to 0
(enabled).
• The channel 3 specified for input signal error detection extended setting is set to
1 (different value of lower and upper limit).
b15
b14 b13 b12 b11 b10
0
0
0
0
0
[Setting example of Q62AD-DGH]
When performing the following settings, store 2332
address 47 (Un\G47).
• The channel 1 specified for the process alarm setting is set to 0 (enabled).
• The channel 1 and 2 specified for input signal error detection are set to 0
(enabled).
• The channel 2 specified for input signal error detection extended setting is set to
1 (different value of lower and upper limit).
b15
b14 b13 b12 b11 b10
0
0
1
0
CH2 CH1
2
b10
b9
b8
CH4 CH3 CH2 CH1
Input signal
error detection
b9
b8
b7
1
0
1
1
1
CH4 CH3 CH2 CH1
CH4 CH3 CH2 CH1
B
b9
b8
b7
0
0
1
1
0
CH2 CH1
3
b7
b6
b5
b4
CH4 CH3 CH2 CH1
CH4 CH3 CH2 CH1
Rate alarm setting
Process alarm setting
0: Enable, 1: Disable
(18942) to the buffer
H
b6
b5
b4
b3
b2
b1
1
1
1
1
1
CH4 CH3 CH2 CH1
F
E
(9010) to the buffer memory
H
b6
b5
b4
b3
b2
0
1
1
0
0
CH2 CH1
CH2 CH1
3
2
MELSEC-Q
b3
b2
b1
b0
b0
1
0
0BFE
(3070)
H
b1
b0
1
0
2332
(9010)
H
3 - 59

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