Mitsubishi MELSEC Q Series User Manual page 62

Channel isolated high resolution analog-digital converter module / channel isolated high resolution analog-digital converter module (with signal conditioning function)
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3
SPECIFICATIONS
Device No.
Signal Name
Channel change
XB
completed flag
Input signal error
XC
detection signal
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(1) This is used as an interlock condition for setting the channel change request (YB) to
ON/OFF when changing the channel for which the offset/gain settings are to be
performed.
(2) See Section 4.6 regarding the offset/gain settings.
Offset/gain setting mode
Offset/gain specifications
(buffer memory addresses 22, 23:
Un\G22, Un\G23)
Channel change completed
flag (XB)
Channel change request (YB)
(1) This signal turns ON when the analog input value falls outside the setting range set to
the Input signal error detection setting value/input signal error detection lower limit
setting value (buffer memory addresses 138 to 141: Un\G138 to Un\G141), Input signal
error detection upper limit setting value (buffer memory addresses 142 to 145: Un\G142
to Un\G145) on any of the channels enabled for A/D conversion after the Input signal
error detection is made valid.
(2) When the Input signal error detection signal (XC) turns ON
1) The A/D conversion completed flag (buffer memory address 10: Un\G10) of the
corresponding channel turns OFF.
2) The digital output value is held as at the time of error detection.
3) The ALM LED flickers.
(3) By bringing the analog input value within the setting range and then turning ON the
Error clear request (YF), the Input signal error detection signal (XC) turns OFF and the
ALM LED is extinguished.
(4) When the analog input value returns to within the setting range, A/D conversion is
resumed independently of whether the Input signal error detection signal (XC) is reset or
not, and after the first updating, the A/D conversion completed flag (buffer memory
address 10: Un\G10) of the corresponding channel turns ON again.
The processing, such as averaging processing or primary delay filter, starts from the first
time after resumption of A/D conversion.
Input signal error detection flag
(Buffer memory address 49:
Un\G49)
Input signal error detection signal
(XC)
Error clear request (YF)
Description
Performed by the A/D converter module
Performed by the sequence program
Performed by the A/D converter module
Performed by the sequence program
Input signal error
0
detection
MELSEC-Q
0
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