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AT8901
3.7.6
Optional Chassis to Logic Ground Connection
According to NEBS requirement R9-14 of GR-1089-CORE issue 3, the AT8901 provides a con-
nection between chassis and logic ground. It is made up of a screw that connects the PCB to
the bottom sheet.
If chassis and logic ground shall be isolated, the screw with its washer can be removed. It is
located near the jumper header J11 and is labelled "GND TO CHASSIS".
3.8
Reset
The reset chain is based on seven elements. The first element in the chain is the voltage supply
monitor, followed by the CPLD, FUM, IPMC, Payload voltage, PPC and Base Interface.
The reset switch will perform a reset on the CPU when pressed for less than 1 second and a
complete board reset (including IPMI) when pressed for more than 2 seconds.
3.9
Jumpers
Five jumpers in the upper right corner allow debug settings (J11). The IPMI override jumpers
enable bypassing communication with the ShMC for bench operation. The JTAG jumpers con-
figure the boundary scan path. JTAG operation requires the use of an RTM.
Warning!
Operation with any of these jumpers set is not supported by the standard appli-
cation software.
Table 3-16: Jumper Settings (
FWPD - Flash Write Enable
Write Enable
•
Write Protect
IPMC0 - Front Board IPMI Override
ShMC Bypass
•
Normal Operation
IPMC1 - AMC IPMI Override
ShMC Bypass
•
Normal Operation
JTAG_AMC - AMC JTAG Integration
Included in JTAG Chain
•
Excluded from JTAG Chain
JTAG_IPMC - IPMC JTAG
Restrict JTAG to IPMC
•
Normal JTAG Operation
•
Default Setting)
in
out
in
out
in
out
in
out
in
out
Page 3 - 17
Hardware Description
AT8901 User Guide
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