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AT8901
4.3.1
Power On Self Test
4.3.1.1
Test Routines
Upon power on or system reset, the bootloader performs a set of Power On Self Tests (POST)
to check the integrity of specific components. Components where a POST is available are:
• SDRAM
• PPC405 serial line
• PPC405 I2C
• PPC405 FE
In the case that a POST fails, a POST error code is written into the postcode high byte register
of the onboard CPLD. The boot process is not stopped as there are good chances the board
can boot even in case of POST errors. The postcode high byte register is also accessible by
the IPMC which can report error codes to a separate management instance. Thus more com-
prehensive diagnostic tests could be started.
The following table shows a list of available POST routines including POST error codes.
Table 4-1:
POST routines and error codes
Device
SDRAM
Data bus - walking 1 test
SDRAM
Address bus - walking 1 test
SDRAM
Memory - read/write test
PPC405 UART
Serial loopback teststring
PPC405 I2C
Bus scan for devices from I2C_ADDR_LIST
PPC405 FE
Phy access
PPC405 FE
Phy loopback test using special Ethernet test frame
KCS
KCS READY signal test
4.3.1.2
Boot Steps
In addition to the Power On Self Tests described above, the bootloader logs the board startup
sequence in the postcode low byte register. A postcode value is written each time a step in the
start sequence has been completed successfully. The postcode stored is also accessible by
the IPMC. In the case that an error occurs during execution of a step, the boot sequence is
stopped because a fatal error has occurred with great likelihood. In this case, a management
instance can read the last postcode written via the IPMC and thus determine where the fatal
error has occurred.
Test
Page 4 - 8
Software Description
POST Error Code
PCW_DLINE
PCW_ALINE
PCW_MEM
PCW_SERIAL
PCW_I2C
PCW_ETH1
PCW_ETH2
KCSCTL
AT8901 User Guide
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