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AT8901
Hardware Description
FUM
The Firmware Update Manager (FUM) is a microcontroller with embedded 16 Kbyte data flash
ROM and 1 Kbyte RAM.
The FUM is responsible for field upgrades, rollbacks and watchdog functions of the IPM con-
troller. Four SPI compatible memory devices are connected to the FUM which build up two IPMI
firmware banks with 512 Kbyte each. One bank contains a copy of the current IPMC code. The
other bank can be written without affecting IPMC operation. Once the bank is updated, the FUM
writes its content into the IPMC. IPMC control signals are all buffered in the CPLD so that board
operation is not affected during update. In the case of a fault during the update process, the
FUM can configure the IPMC with the old firmware that is kept in the other bank. The FUM is
also the watchdog timer for the IPMC. There are several control signals to supervise the IPM
controller.
CPLD
The CPLD is responsible for connecting the PPC to the IPMC and FUM and for handling the
serial interfaces of PPC, IPMC and FUM to the RS232 connector on the front panel. The host
interface between PowerPC and CPLD, realized by PPC's External Bus Interface (EBC), is
used as CPLD-Register-Interface and as communication interface to IPM controller. The EBC
is configured as a demultiplexed 8 Bit Address/Data interface. For accesses to the IPMC Con-
troller, an EBC to LPC (Low Pin Count)-Bridge is included as protocol interface. The LPC inter-
face is for communication between IPMC and PPC over KCS protocol. An additional LPC-IF is
connected to the Fabric mezzanine.
The CPLD controls the LEDs for the whole board via shift registers. It handles the signals to
monitor the AMCs, fabric mezzanine module and the RTM and handles the signals for the line
drivers for the synchronization clocks and the AMC GbE support channels.
An internal multiplexer controls the serial interfaces from the PPC, the FUM and the IPMC. It
is possible to connect each device to the other or to the RS232 connector on the front panel.
3.5
Synchronization Clock
The Synchronization Clock Interface provides three differential pairs per AMC for clock distri-
bution from the AMCs to the Hub Board and vice versa to enable applications that require the
exchange of synchronous timing information among modules and consequently multiple
boards in a shelf. This allows modules to source clock(s) to the system in the case where it
provides a network interface function, or conversely to receive timing information from another
carrier board or module within the system. The three synchronization clock signals are CLK1,
CLK2, and CLK3, each supported by a differential pair. CLK1 and CLK2 are driven by the
AMCs to the backplane and CLK3 will be received from the backplane. AMC1 and 2 cannot
transmit or receive simultaneously signals to or from the backplane. Either the CLK signals of
AMC1 are valid or the CLK signals of AMC2. The Hub Board cannot receive any synchroniza-
tion clocks from other carrier boards, it is only used for distribution. The three differential clock
signals are buffered by three differential line drivers that are controlled by the IPMC and CPLD
respectively.
For further details please refer AMC specification AMC0.RC1.1.
Page 3 - 12
AT8901 User Guide
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