Keithley 2520 User Manual page 23

Pulsed laser diode test system
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C
Data Flow
Figure C-1
Data flow block diagram .......................................................
D
IEEE-488 Bus Overview
Figure D-1
IEEE-488 bus configuration ..................................................
Figure D-2
IEEE-488 handshake sequence .............................................
Figure D-3
Command codes ..................................................................
F
Measurement Considerations
Figure F-1
Model 2520 pulse output circuit model .................................
Figure F-2
Rise time of 4A current pulse ................................................
Figure F-3
Rise time of 0.45A current pulse ...........................................
Figure F-4
Effects of open loop area .......................................................
Figure F-5
Ideal response of 2A pulse using 10 inch cables ...................
Figure F-6
Response of 2A pulse with two square inch loop ..................
Figure F-7
Sense lead connections ..........................................................
Figure F-8
Response of 2A pulse with sense leads 1/4 inch away
from DUT ...........................................................................
Figure F-9
Magnetic coupling ...............................................................
Figure F-10
Optical pulse propagation through differing indices of
refraction ...........................................................................
Figure F-11
Model 2520 output circuit model .........................................
Figure F-12
Minimal impedance mismatch .............................................
Figure F-13
Compromised shield provides laser diode access ................
Figure F-14
Voltage measurement circuit model .....................................
Figure F-15
Pulse source and forward voltage cable interconnections ...
Figure F-16
Model 2520 photo current measurement channels with
dual bias supplies ..............................................................
Figure F-17
Voltage burden .....................................................................
Figure F-18
Eliminating ground loops ....................................................
Figure F-19
Power line ground loops ......................................................
C-2
D-4
D-6
D-11
F-2
F-4
F-5
F-6
F-7
F-7
F-8
F-9
F-10
F-11
F-13
F-14
F-14
F-15
F-15
F-16
F-20
F-21
F-21

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