Eb64H16 Evaluation Board Block Diagram - IDT 89EBPES48H12 Manual

IDT Installation of the EB64H16 Eval Board

EB64H16 Evaluation Board Block Diagram

25MHz
Clock
SSC
Fanout Clock
P14 P15
P. M.
JTAG
Header
Reset
EB64H16 Eval Board Manual
P12 P13 P10 P11 P8
P. M. P. M.
P. M.
64 Lanes / 16 Ports
Figure 2.5 EB64H16 Eval Board Block Diagram
P9 P4 P5
P6
P7
P. M.
P. M.
IDT
2 - 24
USPCTL
Header
P3 P1
P2 P0
P. M. P. M.
Master
SMBus
Slave
SMBus
January 16, 2007
EEPROM
IO EXPs