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IDT 89EBPES24T3G2 Manual

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IDT
89EBPES24T3G2
™
Evaluation Board Manual
(Eval Board: 18-657-000)
January 2008
6024 Silver Creek Valley Road, San Jose, California 95138
Telephone: (800) 345-7015 • (408) 284-8200 • FAX: (408) 284-2775
Printed in U.S.A.
©2008 Integrated Device Technology, Inc.

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Summary of Contents for IDT 89EBPES24T3G2

  • Page 1 ® 89EBPES24T3G2 ™ Evaluation Board Manual (Eval Board: 18-657-000) January 2008 6024 Silver Creek Valley Road, San Jose, California 95138 Telephone: (800) 345-7015 • (408) 284-8200 • FAX: (408) 284-2775 Printed in U.S.A. ©2008 Integrated Device Technology, Inc.
  • Page 2 Integrated Device Technology, Inc. reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply the best possible product. IDT does not assume any responsibility for use of any circuitry described other than the circuitry embodied in an IDT product. The Company makes no representations that circuitry described herein is free from patent infringement or other rights of third parties which may result from its use.

  • Page 3: Table Of Contents

    Table of Contents ® Description of the EB24T3G2 Eval Board Notes Introduction ............................. 1-1 Board Features ..........................1-2 Hardware ..........................1-2 Software..........................1-2 Other............................1-2 Revision History ..........................1-2 Installation of the EB24T3G2 Eval Board EB24T3G2 Installation........................2-1 Hardware Description ........................2-1 Reference Clocks..........................
  • Page 4 IDT Table of Contents Notes EB24T3G2 Eval Board Manual January 21, 2008...
  • Page 5 List of Tables ® Table 2.1 Clock Source Selection ....................... 2-1 Notes Table 2.2 SMA Connectors - Onboard Reference Clock ..............2-2 Table 2.3 External Power Connector - J1 ................... 2-2 Table 2.4 Downstream Reset Selection ..................... 2-3 Table 2.5 Boot Configuration Vector Signals ..................
  • Page 6 IDT List of Tables Notes EB24T3G2 Eval Board Manual January 21, 2008...

  • Page 7: List Of Figures

    List of Figures ® Figure 1.1 Function Block Diagram of the EB24T3G2 Eval Board ............1-1 Notes EB24T3G2 Eval Board Manual January 21, 2008...
  • Page 8 IDT List of Figures Notes EB24T3G2 Eval Board Manual January 21, 2008...

  • Page 9: Description Of The Eb24T3G2 Eval Board

    Introduction Notes The 89HPES24T3G2 switch (also referred to as PES24T3G2 in this manual) is a member of IDT’s PCI Express® standard based line of products. It is a PCIe® Base Specification 2.0 compliant (Gen2) 3-port switch, with 8 serial lanes per port. One x8 upstream port is provided for connecting to the root complex (RC), and two x8 downstream ports are available for connecting to PCIe endpoints or to another switch.

  • Page 10: Board Features

    IDT Description of the EB24T3G2 Eval Board Board Features Notes Hardware PES24T3G2 PCIe 3 port switch – Three x8 ports, 24 PCIe lanes – PCIe Base Specification Revision 2.0 compliant (Gen2 SerDes speeds of 5 GT/S) – Up to 2048 byte maximum Payload Size –...

  • Page 11: Installation Of The Eb24T3G2 Eval Board

    Chapter 2 Installation of the EB24T3G2 Eval Board ® EB24T3G2 Installation Notes This chapter discusses the steps required to configure and install the EB24T3G2 evaluation board. All available DIP switches and jumper configurations are explained in detail. The primary installation steps are: 1.

  • Page 12: Power Sources

    IDT Installation of the EB24T3G2 Eval Board Notes The output of the onboard clock generator is accessible through two SMA connectors located on the Evaluation Board. See Table 2.2. This can be used to connect a scope for probing or capturing purposes and cannot be used to drive the clock from an external source.

  • Page 13: Power-Up Sequence

    IDT Installation of the EB24T3G2 Eval Board Power-up Sequence Notes During power supply ramp-up, VDDCORE must remain at least 1.0V below VDDIO at all times. There are no other power-up sequence requirements for the various operating supply voltages. Reset The PES24T3G2 supports two types of reset mechanisms as described in the PCI Express specifica- tion: –...

  • Page 14: Smbus Interfaces

    IDT Installation of the EB24T3G2 Eval Board Notes Signal Description CCLKDS Common Clock Downstream. The assertion of this pin indicates that all downstream ports are using the same clock source as that provided to downstream devices. This pin is used as the initial value of the Slot Clock Configuration bit in all of the Link Status Registers for downstream ports.

  • Page 15: Smbus Master Interface

    IDT Installation of the EB24T3G2 Eval Board Notes Slave SMBus Interface Connector J8 Signal Table 2.7 Slave SMBus Interface Connector The slave SMBus interface responds to the following SMBus transactions initiated by an SMBus master. Initiation of any SMBus transaction other than those listed above produces undefined results. See the SMBus 2.0 specification for a detailed description of the following transactions:...

  • Page 16: Attention Buttons

    IDT Installation of the EB24T3G2 Eval Board JTAG Header Notes The PES24T3G2 provides a JTAG connector J5 for access to the PES24T3G2 JTAG interface. The connector is a 2.54 x 2.54 mm pitch male 10-pin connector. Refer to Table 2.9 for the JTAG Connector J5 pin out.

  • Page 17: Miscellaneous Jumpers, Headers

    IDT Installation of the EB24T3G2 Eval Board Miscellaneous Jumpers, Headers Notes Miscellaneous Jumpers, Headers Ref. Type Default Description Designator W1-W3 Header 1-2 Shunted 1-2: 12.0V source from Upstream Port (Default) 2-3: 12.0V source from external power connector Header Shunted Disable EEPROM Write protect feature (Default)

  • Page 18: Pci Express Connectors

    IDT Installation of the EB24T3G2 Eval Board Notes Location Color Definition DS23 Green Port 0: Linkup Indicator DS24 Green Port 0: Activity Indicator Port 2: Power Fault Indicator DS10 Port 4: Power Fault Indicator DS25 Green GPIO8 Green GPIO9 DS26...
  • Page 19 IDT Installation of the EB24T3G2 Eval Board Notes Side A Side B PETn1 pair, Lane 1 Ground Ground PERp1 Receiver differential Ground PERn1 pair, Lane 1 PETp2 Transmitter differential Ground PETn2 pair, Lane 2 Ground Ground PERp2 Receiver differential Ground...

  • Page 20: Eb24T3G2 Board Figure

    IDT Installation of the EB24T3G2 Eval Board EB24T3G2 Board Figure Slot 2 Slot 4 EB24T3G2 Eval Board Manual 2 - 10 January 21, 2008...

  • Page 21: Software For The Eb24T3G2 Eval Board

    PCIe parts from IDT. Once users are familiar with the GUI, they will be able to use the same GUI on all PCIe parts from IDT. This software is customized for each device through an XML device description file which includes information on the number of ports, registers, types of registers, information on bit-fields within each register, etc.
  • Page 22 IDT Software for the EB24T3G2 Eval Board Notes EB24T3G2 Eval Board Manual 3 - 2 January 21, 2008...

  • Page 23: Schematics

    Chapter 4 Schematics ® Schematics Notes EB24T3G2 Eval Board Manual 4 - 1 January 21, 2008...
  • Page 24 18-657-000 AUTHOR CHECKED BY CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC. K Leung / T Tran D Huang 6024 SILVER CREEK VALLEY RD. SAN JOSE, CA 95138 COPYRIGHT (C) IDT 2008 Thu Jan 17 16:48:53 2008 SHEET 1 OF 12...
  • Page 25 18-657-000 AUTHOR CHECKED BY CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC. K Leung / T Tran D Huang 6024 SILVER CREEK VALLEY RD. SAN JOSE, CA 95138 COPYRIGHT (C) IDT 2008 Thu Jan 17 16:46:18 2008 SHEET 2 OF 12...
  • Page 26 ALL POWER NETS USE PLANE OR WIDE TRACE AUTHOR CHECKED BY CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC. K Leung / T Tran D Huang 6024 SILVER CREEK VALLEY RD. SAN JOSE, CA 95138 COPYRIGHT (C) IDT 2008 Thu Jan 17 16:46:23 2008 SHEET 3 OF 12...
  • Page 27 18-657-000 AUTHOR CHECKED BY CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC. K Leung / T Tran D Huang 6024 SILVER CREEK VALLEY RD. SAN JOSE, CA 95138 COPYRIGHT (C) IDT 2008 Thu Jan 17 16:46:36 2008 SHEET 4 OF 12...
  • Page 28 18-657-000 AUTHOR CHECKED BY CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC. K Leung / T Tran D Huang 6024 SILVER CREEK VALLEY RD. SAN JOSE, CA 95138 COPYRIGHT (C) IDT 2008 Thu Jan 17 16:46:40 2008 SHEET 5 OF 12...
  • Page 29 18-657-000 AUTHOR CHECKED BY CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC. K Leung / T Tran D Huang 6024 SILVER CREEK VALLEY RD. SAN JOSE, CA 95138 2008 COPYRIGHT (C) IDT Thu Jan 17 16:46:42 2008 SHEET 6 OF 12...
  • Page 30 18-657-000 AUTHOR CHECKED BY CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC. K Leung / T Tran D Huang 6024 SILVER CREEK VALLEY RD. SAN JOSE, CA 95138 2008 COPYRIGHT (C) IDT Thu Jan 17 16:46:47 2008 SHEET 7 OF 12...
  • Page 31 18-657-000 AUTHOR CHECKED BY CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC. K Leung / T Tran D Huang 6024 SILVER CREEK VALLEY RD. SAN JOSE, CA 95138 COPYRIGHT (C) IDT 2008 Thu Jan 17 16:46:50 2008 SHEET 8 OF 12...
  • Page 32 18-657-000 AUTHOR CHECKED BY CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC. K Leung / T Tran D Huang 6024 SILVER CREEK VALLEY RD. SAN JOSE, CA 95138 2008 COPYRIGHT (C) IDT Thu Jan 17 16:46:55 2008 SHEET 9 OF 12...
  • Page 33 18-657-000 AUTHOR CHECKED BY CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC. K Leung / T Tran D Huang 6024 SILVER CREEK VALLEY RD. SAN JOSE, CA 95138 2008 COPYRIGHT (C) IDT Thu Jan 17 16:46:58 2008 SHEET 10 OF 12...
  • Page 34 18-657-000 AUTHOR CHECKED BY CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC. K Leung / T Tran D Huang 6024 SILVER CREEK VALLEY RD. SAN JOSE, CA 95138 COPYRIGHT (C) IDT 2008 Thu Jan 17 16:47:02 2008 SHEET 11 OF 12...
  • Page 35 18-657-000 AUTHOR CHECKED BY CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC. K Leung / T Tran D Huang 6024 SILVER CREEK VALLEY RD. SAN JOSE, CA 95138 2008 COPYRIGHT (C) IDT Thu Jan 17 16:47:05 2008 SHEET 12 OF 12...

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