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Evaluation Board Schematics
Evaluation board schematics are shown on the following pages.
Figure 5. Evaluation Board Schematic (1)
5
4
VDDD
3,4
VDDA_VDDD1
1,3,4
VDDSE1
1,3,4
VDDSE2
1,3,4
VDDSE3
4
VDDDIFF1
4
VDDDIFF2
D
2,3
SDA_DFC0
2,3
SCL_DFC1
Y1
1
3
4
2
GND
GND
25 MHz 8 pF
6.8 pF
C1
6.8 pF
GND
C
J1
CLKIN_CONN
2
1
3
4
5
CON SMA4
J2
CLKINB_CONN
2
1
3
4
5
CON SMA4
B
OE[3:1]
OE[3:1]
Layout notes.
1.Separate Xout and Xin traces
by at least 3 x the trace width.
2.Do not share crystal load
capacitor ground via with
other components.
3.Route power from bead through
A
bulk capacitor pad then
through 0.1uF capacitor pad
then to clock chip Vdd pad.
4.Do not share ground vias. One
ground pin one ground via.
5.Exposed pad should be
grounded but is not required.
5
©2017 Integrated Device Technology, Inc.
4
VBAT_PS VDDD
VDDA
U1
5P53023
1
VDDA
9
VDDD
6
VBAT
CLKIN
4
CLKIN/X1
CLKINB
5
CLKINB/X2
SDA_DFC0
2
SDA/DFC0
SCL_DFC1
3
SCL/DFC1
OE1
15
OE1
CLKIN
OE2
10
OE2
OE3
21
OE3
CLKINB
7
NC
C2
1
R5
2
CLKIN
0_NP
1
R6
2
49.9_NP
1
R7
2
49.9_NP
1
R8
2
CLKINB
0_NP
OE1
OE2
OE3
VBAT_PS
0.1 uF
GND
Locate near U1.6
4
VersaClock
3
13
VDDSE1
14
SER1
1
SE1
R1
11
VDDSE2
12
SER2
1
SE2
R2
20
VDDSE3
19
SER3
1
SE3
R3
8
SER4
1
REF
R4
16
VDDDIFF1
18
DIFFRT1
DIFF1
17
DIFFRC1
DIFF1B
22
VDDDIFF2
24
DIFFRT2
DIFF2
23
DIFFRC2
DIFF2B
Locate near DUT
power pin
VDDDIFF1
VDDSE1
VDDA_VDDD1
C30
C31
0.1 uF
0.1 uF
VDDDIFF2
VDDSE2
C33
C34
0.1 uF
0.1 uF
VDDSE3
C37
0.1 uF
C25
C26
10 uF
LOGO1
3
6
®
3S - 5P35023 Evaluation Board User Manual
2
VDDSE1
1,3,4
VDDSE1
2
SE_1
33
VDDSE2
VDDSE2
1,3,4
VDDSE2
2
SE_2
33
VDDSE3
VDDSE3
1,3,4
VDDSE3
2
SE_3
33
2
SE_4
33
VDDDIFF1
VDDDIF1
R79
1
2
33
DIFF_T1
R80
1
2
33
DIFF_C1
VDDDIFF2
VDDDIF2
R81
1
2
33
DIFF_T2
R82
1
2
33
DIFF_C2
DIFF_C[2:1]
DIFF_C[2:1]
FB4
R59
1
2
Node#3
1
2
BLM18AG601SN1D
2.2
C42
0.1 uF
FB5
1
BLM18AG601SN1D
C53
0.1 uF
Integrated Device Technology
Integrated Device Technology
Integrated Device Technology
San Jose, CA
San Jose, CA
San Jose, CA
Size
Size
Size
Document Number
Document Number
Document Number
A
A
A
5L35023/5P35023
5L35023/5P35023
5L35023/5P35023
Date:
Date:
Date:
Friday, November 04, 2016
Friday, November 04, 2016
Friday, November 04, 2016
2
1
D
4
SE_[4:1]
SE_[4:1]
DIFF_T[2:1]
4
DIFF_T[2:1]
DIFF_T[2:1]
C
DIFF_C[2:1]
VDDA
C43
C48
10 uF
0.1 uF
B
GND
VDDD
2
C50
0.1 uF
C54
10 uF
GND
A
R e v
R e v
R e v
C1
C1
C1
Sheet
Sheet
Sheet
1
1
1
o f
o f
o f
4
4
4
1
June 8, 2017
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