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82P33714/33814 Evaluation Board
Introduction
The 82P33714/33814 evaluation board is designed to help the customer evaluate the IDT82P33714 and IDT82P33814 devices.
This user guide will accomplish the following:
•
Introduce the board on its power supply and jumper settings
•
Describe the input and output connectors for normal operation
•
How to bring up the board by using Timing Commander software GUI
•
How to configure and program the board to generate standard-compliant frequencies
Board Overview
Use
Figure 1
to identify various components of the board: Input and output SMA connectors; Power supply jacks and some
jumper settings necessary for the board operations. Detailed descriptions are as follows:
•
Input SMA Connectors – There are a total of 6 inputs, of which IN5 and IN6 are single-ended inputs; IN1, 2, 3, 4 are
differential inputs.
•
Output SMA Connectors – There are a total of 10 outputs, of which OUT1, 2, 7, 8, 9, 10 are single-ended outputs; OUT3, 4,
5, 6 are differential outputs. MFR_2K_1PPS and MFR_8K_1PPS are single-ended outputs providing 2KHz and 8KHz frame
sync signals, respectively.
•
USB connector – Type-B connector for GUI communications. No power is drawn from USB connector other than to power
the FTDI USB chip.
•
Dip Switch SW6 – Used to configure EEPROM write protection, master or slave selection and communication protocols
between PC/GUI and the board. For typical I
•
J76 – This is a 2x12 pin header used to set communication mode between the PC and the board.
the header pairs for the intended mode. By default, I
Table 1: Using the J76 Header to Set the Communication Between the PC and the Board
FTDI SPI
Aardvark SPI/I2C
3-4 Jumper
1-3 Jumper
9-10 Jumper
7-9 Jumper
15-16 Jumper
13-15 Jumper
21-22 Jumper
19-21 Jumper
REVISION A 09/15/14
2
C mode, set MPU_MODE[1:0] = 00 ('I2C ON').
2
C mode will be selected with JP18 shunted (jumped).
FTDI I2C
Motherboard SPI/I2C
3-4 Jumper
3-5 Jumper
9-10 Jumper
9-11 Jumper
14-16 Jumper
15-17 Jumper
21-23 Jumper
1
USER GUIDE
Table 1
shows how to jump
FTDI UART
FTDI to Aardvark
4-6 Jumper
1-2 Jumper
9-10 Jumper
7-8 Jumper
15-16 Jumper
13-14 Jumper
19-20 Jumper
©2014 Integrated Device Technology, Inc.
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Related Manuals for IDT 82P33714
Summary of Contents for IDT 82P33714
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Page 1: Board Overview
82P33714/33814 Evaluation Board USER GUIDE Introduction The 82P33714/33814 evaluation board is designed to help the customer evaluate the IDT82P33714 and IDT82P33814 devices. This user guide will accomplish the following: • Introduce the board on its power supply and jumper settings •... - Page 2 82P33714/33814 EVALUATION BOARD Figure 1. Board Overview • OSCI Input and XO – System reference clock input. Refer to JP9 for clock source selection. The frequency of this input clock is selected by XO_FREQ[2:0] pins described in SW5. • HW Reset button – Pressing this button will reset the device to default condition.
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Page 3: Board Power Supply
82P33714/33814 EVALUATION BOARD Board Power Supply There are two ways to power up the board: • Use an AC/DC adapter which provides 5VDC to on-board voltage regulators to generate 3.3V and 1.8V. • Connect a 5VDC power source (i.e., a bench power supply) to the power jack that is labeled s “5V”. -
Page 4: Board Default Frequency Output
82P33714/33814 EVALUATION BOARD Board Default Frequency Output Upon power-up, the following default frequencies will be available: • OUT1 = 25MHz • OUT2 = 125MHz • OUT3 = 156.25MHz • FRSYNC_8K_1PPS = 8kHz • MFRSYNC_2K_1PPS = 2KHz Working with TimingCommand for Configuration Use the following steps to setup the board using I C and start the configuration of the board. - Page 5 82P33714/33814 EVALUATION BOARD Figure 4. Selecting the Correct Device – 82P33814 is Selected. Open a Personality File 5. The GUI window is open for configurations. Overall, the configuration window shows 6 inputs on the left and 10 outputs are on the right side of the window. For Input configuration, most frequencies can be entered for IN01 ~ IN6 and they will be automatically configured to be available to both DPLLs.
- Page 6 82P33714/33814 EVALUATION BOARD Figure 5. Enter Input and Output Frequencies To associate an input clock with a sync signal (such as 1PPS, for e)xample, to associate a sync signal IN1 (1PPS) to IN02 (10MHz)), click on the Input Buffer of IN02 (the triangle symbol following frequency entry box), a sub-configuration window for IN02 is shown below.
- Page 7 82P33714/33814 EVALUATION BOARD Figure 7. IN01 is Disabled as an Input Clock to DPLL (orange oval) because it's only used as a sync signal for IN02 6. Each DPLL has Profile Selection and a “Configure” button. In general, the pull-down Profile Selection should be sufficient to automatically pre-configure the DPLL and reference monitor for the specific ITU-T recommendation.
- Page 8 82P33714/33814 EVALUATION BOARD Figure 8. DPLL Configuration Window – Operation Mode Settings In “Bandwidth and Damping” section, there are two options to select DPLL's bandwidth and damping factors during start, acquisition and locked phases: ◦ Always use Locked bandwidth/damping. This option will use the bandwidth and damping factor that are available when DPLL is locked;...
- Page 9 82P33714/33814 EVALUATION BOARD Figure 9. DPLL Configuration Window - Bandwidth/Damping Factor Settings 7. Output Configuration. Most output frequencies can be entered for OUT01~OUT11 and they will be automatically configured. However, 19.2MHz and 10MHz-based clocks are not supported by the default hardware profiles for the APLLs.
- Page 10 82P33714/33814 EVALUATION BOARD Figure 11. APLL1 Parameters for VCO = 614.4MHz ◦ To configure APLL2, select “(custom on DPLL1)” as shown in Figure 10. Then click on “Customize” button and ignore the initial Timing Commander error. Enter the values as shown in Figure 12 below.
- Page 11 82P33714/33814 EVALUATION BOARD Figure 13. Output Frequencies Entered after APLL1/APLL2 Configured (example) ◦ Finally, FRSYNC & MRFRSYNC can be configured, if needed. Change FRSYNC & MFRSYNC to 1PPS. By default, the duty cycle of sync outputs is 50/50. If a pulse is desired, click on the applicable check box. The pulse width is based on OUT01 clock period.
- Page 12 82P33714/33814 EVALUATION BOARD Figure 15. Steps to Making Connections to the Board 9. For each DPLL, there are several frequency profiles to choose from by pull-down menu. These frequency profiles are (see Figure 16 below). ◦ G.8262 Option 1: to configure the DPLL for SyncE for Europe ◦...
- Page 13 82P33714/33814 EVALUATION BOARD Figure 16. Frequency Profiles for DPLL 10.Viewing Status – After writing all registers, with configured input reference clocks available, the PLL is supposed to lock to the reference clock. The PLL operation status can be updated and viewed by clicking “View Status” button in GUI window.
- Page 14 82P33714/33814 EVALUATION BOARD Figure 17. DPLL Status Window REVISION A 09/15/14...
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Page 15: Board Schematics
82P33714/33814 EVALUATION BOARD Board Schematics Figure 18. 82P33x14 Evaluation Board Schematics - Page 1: Block Diagram REVISION A 09/15/14... - Page 16 82P33714/33814 EVALUATION BOARD Figure 19. 82P33x14 Evaluation Board Schematics - Page 2: Reference Selection REVISION A 09/15/14...
- Page 17 82P33714/33814 EVALUATION BOARD Figure 20. 82P33x14 Evaluation Board Schematics - Page 3: I/O Termination REVISION A 09/15/14...
- Page 18 82P33714/33814 EVALUATION BOARD Figure 21. 82P33x14 Evaluation Board Schematics - Page 4: I2C/EEPROM REVISION A 09/15/14...
- Page 19 82P33714/33814 EVALUATION BOARD Figure 22. 82P33x14 Evaluation Board Schematics - Page 5: Power Supply 1 REVISION A 09/15/14...
- Page 20 82P33714/33814 EVALUATION BOARD Figure 23. 82P33x14 Evaluation Board Schematics - Page 6: Power Supply 2 REVISION A 09/15/14...
- Page 21 IDT or any third parties. IDT’s products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users.
- Page 22 Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: IDT (Integrated Device Technology) 82EBP33814...