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Integrated Device Technology, Inc. reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply the best possible product. IDT does not assume any responsibility for use of any circuitry described other than the circuitry embodied in an IDT product. The Company makes no representations that circuitry described herein is free from patent infringement or other rights of third parties which may result from its use.
SAS or SATA cables and a different board with PCIe slots known as the 12-PACK board (provided by IDT). Given that majority of the hosts / servers offer PCIe standard slots, IDT provides the necessary adapter cards that may be plugged into these host / server slots as well as the cables that connect such adapters to the daughter cards which in turn are plugged into the main evaluation board on which the IDT PCIe switch device is populated.
IDT Description of the EB-LOGAN-19 Evaluation Board Board Features Notes Hardware PES24NT24G2 PCIe 24-port switch – Twenty four ports (each x1) - for port 8 and higher, adjacent ports may be combined to create x2, x4 or x8 ports – PCIe Base Specification Revision 2.1 compliant (Gen2 SerDes speeds of 5 GT/S) –...
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IDT Description of the EB-LOGAN-19 Evaluation Board Notes April 23, 2010: Updated Schematics in Chapter 4. February 16, 2011: Changed default settings from Off to On in Tables 2.3 and 2.4. 89EB-LOGAN-19 Evaluation Board 1 - 3 February 16, 2011...
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IDT Description of the EB-LOGAN-19 Evaluation Board Notes 89EB-LOGAN-19 Evaluation Board 1 - 4 February 16, 2011...
The EB-LOGAN-19 board is typically shipped with all jumpers and switches configured to their default settings. In most cases, the board does not require further modification or setup however please visit IDT website and fill out the Technical Support Request form at http://www.idt.com/?app=TechSupport for other configurations.
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IDT Installation of the EB-LOGAN-19 Evaluation Board Notes Pictured in Figure 2.2 is the mini-SAS Mezzanine card which consists of two iSAS and two SATA connectors. Each iSAS connector supports up to PCI Express x4 width and the SATA connectors are used for clock and reset signals of each x4 or less stack/port.
IDT Installation of the EB-LOGAN-19 Evaluation Board Notes Figure 2.4 PCIe x1 Edge-to-SATA Adapter Hardware Description The PES24NT24G2 is a 24-lane, 24-port PCI Express® switch. It is a peripheral chip that performs PCI Express based switching with a feature set optimized for high performance applications such as servers and storage.
IDT Installation of the EB-LOGAN-19 Evaluation Board Notes 8-P IN EPS 12V 8-P IN EPS 12V 24-PIN ATX 24-PIN ATX +3.3 +3.3 clk[0:11] clk[0:11] 1:12 1:12 On-Board On-Board Clock Gen Clock Gen Buffer Buffer SATA SATA Data Data Data Data...
IDT Installation of the EB-LOGAN-19 Evaluation Board Notes Figure 2.8 Reference Clock Configuration By default the clock buffer derives its clock from a common source. The common source can be the host system’s reference clock, the onboard clock generator, or SATA connector (J8). See Table 2.2.
IDT Installation of the EB-LOGAN-19 Evaluation Board Notes Onboard Clock Frequency Switch - S10[1] S10[1] Clock Frequency 100 MHz (Default) 125 MHz Table 2.4 Onboard Clock Generator Frequency Select The output of the onboard clock generator is accessible through two yellow colored loop connectors located on the Evaluation Board.
IDT Installation of the EB-LOGAN-19 Evaluation Board Notes Signal Signal PWR_OK 5VSB +12V3 +12V3 +3.3V Table 2.9 EPS12V 24-pin Power Connector - J6 (Part 2 of 2) Signal Signal +12V1 +12V1 +12V2 +12V2 Table 2.10 EPS12V 8-Pin Connector - J5 The power on switch located at S1 can be used to control the supply power from the external power supply connector.
IDT Installation of the EB-LOGAN-19 Evaluation Board Reset Notes The PES24NT24G2 supports two types of reset mechanisms as described in the PCI Express specifica- tion: – Fundamental Reset: This is a system-generated reset that propagates along the PCI Express tree through a single side-band signal PERST# which is connected to the Root Complex, the PES24NT24G2, and the endpoints.
IDT Installation of the EB-LOGAN-19 Evaluation Board Notes Slave Interface Address Configuration Address Bit Signal SSMBUSADDR[1] SSMBUSADDR[2] Table 2.15 SMBus Slave Interface Address Configuration The slave SMBus interface responds to the following SMBus transactions initiated by an SMBus master. Initiation of any SMBus transaction other than those listed above produces undefined results. See the SMBus 2.0 specification for a detailed description of the following transactions:...
IDT Installation of the EB-LOGAN-19 Evaluation Board PCI Express Connectors Notes Side A Side B +12V 12V power PRSNT1# Hot-Plug presence detect +12V 12V power +12V 12V power RSVD Reserved +12V 12V power Ground Ground SMCLK SMBus clock JTAG2 TCK (Test Clock) JTAG i/f clk i/p...
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IDT Installation of the EB-LOGAN-19 Evaluation Board Notes Side A Side B PETn4 pair, Lane 4 Ground Ground PERp4 Receiver differential Ground PERn4 pair, Lane 4 PETp5 Transmitter differential Ground PETn5 pair, Lane 5 Ground Ground PERp5 Receiver differential Ground...
PCIe parts from IDT. Once users are familiar with the GUI, they will be able to use the same GUI on all PCIe parts from IDT. This software is customized for each device through an XML device description file which includes information on the number of ports, registers, types of registers, information on bit-fields within each register, etc.
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IDT Software for the EB-LOGAN-19 Eval Board Notes 89EB-LOGAN-19 Evaluation Board 3 - 2 February 16, 2011...
+3V3 +3V3 PLACE RESISTORS ON CLOSE AND ON SAME SIDE OF BOARD +3V3 MAX7311AUG MAX7311AUG PLACE RESISTORS ON CLOSE AND P0_APN P2_APN ON SAME SIDE OF BOARD P0_PDN P2_PDN 29 37 29 37 P0_PFN P2_PFN 30 37 30 37 P0_PWRGDN 2.7K P2_PWRGDN 30 37...
+3V3 +3V3 PLACE RESISTORS ON CLOSE AND PLACE RESISTORS ON CLOSE AND ON SAME SIDE OF BOARD ON SAME SIDE OF BOARD +3V3 +3V3 MAX7311AUG MAX7311AUG P1_APN P10_APN P1_PDN P10_PDN 29 37 29 37 P1_PFN P10_PFN 30 37 30 37 P1_PWRGDN 2.7K P10_PWRGDN...
+3V3 +3V3 PLACE RESISTORS ON CLOSE AND ON SAME SIDE OF BOARD +3V3 PLACE RESISTORS ON CLOSE AND MAX7311AUG MAX7311AUG ON SAME SIDE OF BOARD P9_APN P17_APN P9_PDN P17_PDN 29 37 29 37 R107 P9_PFN R119 P17_PFN 30 37 30 37 R108 P9_PWRGDN 2.7K...
+3V3 +3V3 PLACE RESISTORS ON CLOSE AND PLACE RESISTORS ON CLOSE AND ON SAME SIDE OF BOARD ON SAME SIDE OF BOARD +3V3 +3V3 MAX7311AUG MAX7311AUG P0_MRLN P0_ILOCKST P1_MRLN P2_ILOCKST R1148 P2_MRLN R1160 P4_ILOCKST R1149 P3_MRLN 2.7K R1161 P6_ILOCKST P4_MRLN P8_ILOCKST 2.7K R1150...
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+3V3 +3V3 PLACE RESISTORS ON CLOSE AND ON SAME SIDE OF BOARD PLACE RESISTORS ON CLOSE AND MAX7311AUG MAX7311AUG ON SAME SIDE OF BOARD P9_ILOCKST P0_ACTIVEN P11_ILOCKST P1_ACTIVEN R1124 P13_ILOCKST R1136 P2_ACTIVEN R1125 P15_ILOCKST R1137 P3_ACTIVEN P17_ILOCKST P4_ACTIVEN R1126 R1138 P19_ILOCKST P5_ACTIVEN P21_ILOCKST...
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+3V3 PLACE RESISTORS ON CLOSE AND ON SAME SIDE OF BOARD MAX7311AUG P0_RSTN 8 16 32 P2_RSTN 8 16 32 R131 P4_RSTN 8 16 32 R132 P6_RSTN 8 16 32 P8_RSTN R133 8 16 32 P12_RSTN 8 16 32 P16_RSTN 8 16 32 P20_RSTN 8 16 32...
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+3V3 +3V3 (RED) ACTIVE LOW - POWER FAULT (GREEN) ACTIVE LOW - POWER GOOD P23_PFN P23_PWRGDN R663 PORT 23 R687 DS29 PORT 23 P22_PFN P22_PWRGDN R664 PORT 22 R688 DS30 PORT 22 P21_PFN P21_PWRGDN R665 PORT 21 R689 DS31 PORT 21 P20_PFN P20_PWRGDN R666...
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+3V3 +3V3 (ORANGE) ACTIVE LOW - ATTENTION OUTPUT (GREEN) ACTIVE LOW - POWER INDICATOR P23_AIN P23_PIN R900 DS206 PORT 23 R924 DS230 PORT 23 P22_AIN P22_PIN R901 DS207 PORT 22 R925 DS231 PORT 22 P21_AIN P21_PIN R902 DS208 PORT 21 R926 DS232 PORT 21...
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+3V3 (GREEN) ACTIVE HIGH - POWER ENABLE (RED) ACTIVE LOW - HP SLOT RST P23_PEP P23_RSTN R711 DS53 PORT 23 R735 DS77 PORT 23 P22_PEP P22_RSTN R712 DS54 PORT 22 R736 DS78 PORT 22 P21_PEP P21_RSTN R713 DS55 PORT 21 R737 DS79 PORT 21...
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+3V3 (GREEN) ACTIVE HIGH - INTERLOCK INPUT (RED) ACTIVE LOW - MRL P23_ILOCKST P23_MRLN R948 DS254 PORT 23 R972 DS278 PORT 23 P22_ILOCKST P22_MRLN R949 DS255 PORT 22 R973 DS279 PORT 22 P21_ILOCKST P21_MRLN R950 DS256 PORT 21 R974 DS280 PORT 21 P20_ILOCKST P20_MRLN...
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+3V3 +3V3 (RED) ACTIVE LOW - PARTITION FUND. RESET (RED) ACTIVE LOW - SLOT HEADER RESET PART7_PERSTN SLOT_HDR_RSTN20 R1020 DS326 PART 7 R1650 DS415 SLOT 20 PART6_PERSTN SLOT_HDR_RSTN16 R1021 DS327 PART 6 R1651 DS416 SLOT 16 PART5_PERSTN SLOT_HDR_RSTN12 R1022 DS328 PART 5 R1652 DS417...
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+3V3 +3V3 (GREEN) ACTIVE LOW - LINK UP (BLUE) ACTIVE LOW - LINK ACTIVITY P23_LINKUPN P23_ACTIVEN R1172 DS334 PORT 23 R1196 DS358 PORT 23 549R BLUE P22_LINKUPN P22_ACTIVEN R1173 DS335 PORT 22 549R R1197 DS359 BLUE PORT 22 P21_LINKUPN P21_ACTIVEN R1174 DS336 PORT 21...
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MINIMUM POWER SUPPLY LOADS +12V1_PS +12V2_PS +12V2_PS +12V2_PS +12V2_PS +12V2_PS +12V2_PS +12V3_PS +12V3_PS +12V3_PS +12V3_PS +12V3_PS +12V3_PS +3V3_PS +3V3_PS +5V0_PS +5V0_PS +5V0_PS EB-LOGAN-19 TITLE MIN LOAD RESISTORS SIZE DRAWING NO. FAB P/N REV. SCH-PESEB-002 18-692-000 AUTHOR CHECKED BY CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC. Tony Tran Derek Huang 6024 SILVER CREEK VALLEY ROAD.
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