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IDT 89EBPES12N3 Evaluation Board Manual

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IDT
89EBPES12N3
™
Evaluation Board Manual
(Eval Board: 18-597-001)
November 2006
6024 Silver Creek Valley Road, San Jose, California 95138
Telephone: (800) 345-7015 • (408) 284-8200 • FAX: (408) 284-2775
Printed in U.S.A.
©2006 Integrated Device Technology, Inc.

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Summary of Contents for IDT 89EBPES12N3

  • Page 1 89EBPES12N3 ™ Evaluation Board Manual (Eval Board: 18-597-001) November 2006 6024 Silver Creek Valley Road, San Jose, California 95138 Telephone: (800) 345-7015 • (408) 284-8200 • FAX: (408) 284-2775 Printed in U.S.A. ©2006 Integrated Device Technology, Inc.
  • Page 2 Integrated Device Technology, Inc. reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply the best possible product. IDT does not assume any responsibility for use of any circuitry described other than the circuitry embodied in an IDT product. The Company makes no representations that circuitry described herein is free from patent infringement or other rights of third parties which may result from its use.

  • Page 3: Table Of Contents

    Table of Contents 1 Description of the EB12N3 Eval Board Notes Introduction ..........................1-1 Board Features ..........................1-2 Hardware..........................1-2 Software ..........................1-2 Other ..........................1-2 Revision History...........................1-3 2 Installation of the EB12N3 Eval Board EB12N3 Installation ........................2-1 Hardware Description ........................2-1 Host System ........................2-1 Reference Clocks ........................2-3 Power Sources ..........................2-4 External Power Source.......................2-4 PCI Express Serial Data Transmit Termination Voltage Regulator........2-4...
  • Page 4 IDT Table of Contents Notes EB12N3 Eval Board Manual (18-597-001) November 2, 2006...
  • Page 5 List of Tables Table 2.1 Clock Source Selection.....................2-3 Notes Table 2.2 Clock Frequency Selection ....................2-3 Table 2.3 Clock Spread Spectrum Selection ..................2-3 Table 2.4 SMA Connectors - Onboard Reference Clock..............2-3 Table 2.5 Power Connector Pin-Out....................2-4 Table 2.6 Power Selection for Downstream Ports Jumpers, Headers..........2-5 Table 2.7 W13 Shunt Selection for Cold Reset ................2-6 Table 2.8...
  • Page 6 IDT List of Tables Notes EB12N3 Eval Board Manual (18-597-001) November 2, 2006...
  • Page 7 List of Figures Figure 1.1 Functional Block Diagram of the EB12N3 Eval Board............1-1 Notes Figure 2.1 SuperMicro X6DH8-G2 Motherboard ................2-2 EB12N3 Eval Board Manual (18-597-001) November 2, 2006...
  • Page 8 IDT List of Figures Notes EB12N3 Eval Board Manual (18-597-001) November 2, 2006...

  • Page 9: Introduction

    PES12N3 chip, and it can also play an important role for customers to get a headstart on software development while they await the arrival of their own hardware. It is also used inside IDT to reproduce system level hardware or software issues reported by customers. Figure 1.1 illustrates the functional block diagram representing the main parts of the EB12N3 board.

  • Page 10: Board Features

    IDT Description of the EB12N3 Eval Board Board Features Board Features Notes Hardware PES12N3 PCIe 3 port switch – Three x4 ports, 12 PCIe lanes – PCIe Base Specification Revision 1.0a compliant – 48 Gbps aggregate switching capacity – 128 to 2048 byte maximum payload size –...

  • Page 11: Revision History

    IDT Description of the EB12N3 Eval Board Revision History Revision History Notes September 26, 2006: Initial publication of board manual. November 2, 2006: Added footnote to Table 2.10 regarding default setting for switch mode pins. EB12N3 Eval Board Manual (18-597-001)
  • Page 12 IDT Description of the EB12N3 Eval Board Revision History Notes EB12N3 Eval Board Manual (18-597-001) 1 - 4 November 2, 2006...

  • Page 13: Installation Of The Eb12N3 Eval Board

    The PES12N3 has two PCI Express x4 downstream ports accessible through two x4 connectors. Each port is capable of negotiating a x1, x2, or x4 link width. All endpoint cards connected to the 89EBPES12N3 must support at least one of these link widths.
  • Page 14 IDT Installation of the EB12N3 Eval Board Hardware Description Notes Figure 2.1 SuperMicro X6DH8-G2 Motherboard EB12N3 Eval Board Manual (18-597-001) 2 - 2 November 2, 2006...

  • Page 15: Reference Clocks

    IDT Installation of the EB12N3 Eval Board Reference Clocks Reference Clocks Notes The EB12N3 requires two differential reference clocks. The EB12N3 drives both of these clocks from a common source. The source for the reference clock is user-selectable between the host system’s reference clock and the onboard clock generator.

  • Page 16: Power Sources

    IDT Installation of the EB12N3 Eval Board Power Sources Power Sources Notes The EB12N3 and all attached endpoint cards are powered entirely by the host system through the upstream PCI Express edge connector. In general, this is sufficient and there is no need for an external power-source.

  • Page 17: Power Selection For Downstream Ports

    IDT Installation of the EB12N3 Eval Board Power Selection for Downstream Ports Power Selection for Downstream Ports Notes The following table illustrates the power selection features and hot plug capabilities for downstream ports B and C. Power Selection for Downstream Ports Jumpers, Headers Ref.

  • Page 18: Reset

    IDT Installation of the EB12N3 Eval Board Reset Reset Notes The PES12N3 supports two types of reset mechanisms as described in the PCI Express specifications: Fundamental Reset: This is a system generated reset that propagates along the PCI Express tree through a single side-band signal PERST#, connected to the Root Complex, the PES12N3 and the endpoints.

  • Page 19: Boot Configuration Vector

    IDT Installation of the EB12N3 Eval Board Boot Configuration Vector Notes Port# Header Selection [1-2] PGOOD_B_N controlled reset (used when hot-plugging is enabled) [3-4] Software controlled reset through GPIO0 [5-6] Fundamental reset PERST# (default) [1-2] PGOOD_C_N controlled reset (used when hot-plugging is enabled)

  • Page 20: Table 2.10 Boot Configuration Vector Signals

    IDT Installation of the EB12N3 Eval Board Boot Configuration Vector Notes Boot Configuration Vector Signals Signal Description RSTHALT Reset Halt. When this signal is asserted during a PCI Express fundamental reset, the PES12N3 executes the reset procedure and remains in a reset state with the Master and Slave SMBuses active.

  • Page 21: Smbus Interfaces

    IDT Installation of the EB12N3 Eval Board SMBus Interfaces Notes Boot Configuration Vector Switches J1 & J2 (ON=0, Off=1) Switch BCV Bit Default J2[4] SWMODE[2] J2[5] SWMODE[3] J2[8] <RESERVED> Table 2.11 Boot Configuration Vector Switches (Part 2 of 2) SMBus Interfaces The PES12N3 contains two SMBus interfaces: a slave SMBus interface and a master SMBus interface.

  • Page 22: Smbus Master Interface

    IDT Installation of the EB12N3 Eval Board SMBus Interfaces Notes Slave Interface Address Configuration Address Bit Signal SSMBUSADDR[5] Table 2.13 SMBus Slave Interface Address Configuration (Part 2 of 2) SMBUS Slave Interface Address Setting Slave Interface Bus Address SSMBADDR[2] SSMBADDR[1]...

  • Page 23: Table 2.15 I/O Expander Address Setting

    IDT Installation of the EB12N3 Eval Board SMBus Interfaces Notes I/O Expander SMBus Address Setting Bus Address 0b0100 111 0b0100 110 0b0100 101 0b0100 100 0b0100 011 0b0100 010 0b0100 001 0b0100 000 (Default) Table 2.15 I/O Expander Address Setting The lower three bits of the bus address for the selected EEPROM device is 0b000 by default and is configurable using the jumpers W15, W17, and W21 as described in Table 2.16.

  • Page 24: Jtag Header

    IDT Installation of the EB12N3 Eval Board JTAG Header JTAG Header Notes The PES12N3 provides a JTAG connector J4 for access to the PES12N3 JTAG interface. The connector is a 2.54 x 2.54 mm pitch male 10-pin connector. Refer to Table 2.18 for the JTAG Connector J4 pin out.

  • Page 25: Pci Express Connector

    IDT Installation of the EB12N3 Eval Board PCI Express Connector Notes Green Port C: Power Indicator Yellow Port C: Attention Indicator Hot Plug Controller: Power Fault Indicator DS10 Green Board Power Indicator (3.3V) DS11 Board Reset Indicator Table 2.20 LED Status Indicators (Part 2 of 2)
  • Page 26 IDT Installation of the EB12N3 Eval Board PCI Express Connector Notes Side A Side B PETp3 Transmitter differential Ground PETn3 pair, Lane 3 Ground Ground PERp3 Receiver differential RSVD Reserved PERn3 pair, Lane 3 PRSNT2# Hot-Plug presence detect Ground Ground...

  • Page 27: Locations Of Connectors, Jumpers, And Switches

    IDT Installation of the EB12N3 Eval Board Locations of Connectors, Jumpers, and Switches Locations of Connectors, Jumpers, and Switches Notes EB12N3 Eval Board Manual (18-597-001) 2 - 15 November 2, 2006...
  • Page 28 IDT Installation of the EB12N3 Eval Board Locations of Connectors, Jumpers, and Switches Notes EB12N3 Eval Board Manual (18-597-001) 2 - 16 November 2, 2006...

  • Page 29: Software For The Eb12N3 Eval Board

    PCIe parts from IDT. Users once familiar with the GUI will be able to use the same GUI on all PCIe parts from IDT. Use of the software is customized for each device through a XML device description file which include information on number of ports, registers, types of registers, information on bit-fields within each register, etc.
  • Page 30 IDT Software for the EB12N3 Eval Board Device Management Software Notes EB12N3 Eval Board Manual (18-597-001) 3 - 2 November 2, 2006...

  • Page 31: Schematics

    Chapter 4 Schematics Schematics Notes EB12N3 Eval Board Manual (18-597-001) 4 - 1 November 2, 2006...
  • Page 32 CR-1 : @TEST4_LIB.\89EBPES12N3\(SCH_1):PAGE1 REVISIONS DESCRIPTION DATE CHANGE BY STGC-0087R01 89EBPES12N3 RESPIN (CREATED) 2006-06-15 K. LEUNG STGC-0087R01 89EBPES12N3 RESPIN (RELEASED) 2006-09-07 K. LEUNG 89EBPES12N3 EVALUATION BOARD SHEET DESCRIPTION TITLE PAGE, BLOCK DIAGRAM POWER, RESET CLOCK EEPROM, SMBUS, JTAG, I/O EXPANDER HOT PLUG CONTROLLER...
  • Page 33 CR-2 : @TEST4_LIB.\89EBPES12N3\(SCH_1):PAGE2 3_3V 3_3V 3_3V 3_3V 3_3V HDR_1X3_100 BOARD RESET E_PERSTN PB_SW TLC7733D 10A5< 9D7< 10C5< RESINN DS11 SENSE RESET CONTROL RESETN PERST* 2C8< 7C3> PERST* 2D4< 7C3> SN74LVC1G125 POWER INDICATOR PLACE NEAR TOP EDGE LABEL 'POWER' 3_3V 12_0VC...
  • Page 34 CR-3 : @TEST4_LIB.\89EBPES12N3\(SCH_1):PAGE3 3_3V 120OHM 0805 3_3V PLEASE RESISTORS CLOSE TO U6 3_3V U_REFCLK+ 7C3> ICS9DB401yGLF 0402 U_REFCLK- 7C3> 4 RP8 0402 3 RP8 VDDA 2 RP8 1 RP8 0402 R109 SRC_IN DIF_1 B_REFCLKP 6C5< R110 B_REFCLKN SRC_IN# DIF_1# 6C5<...
  • Page 35 CR-4 : @TEST4_LIB.\89EBPES12N3\(SCH_1):PAGE4 3_3V 3_3V 3_3V 3_3V PLACE EEPROM ON SOCKET INTERLOCK NOT USED IN 1.0A 3_3V PCA9555 E_GPIO2 9B5<> INT# E_SCL 4C8< 9B8<> E_SDA 4C8< 9B8<> PCAPN 4A4> PBAPN I/O0.0 I/O1.0 4A3> 3_3V 24LC512 6B8> B_PRSNT2# C_PRSNT2# I/O0.1 I/O1.1 6B4>...
  • Page 36 CR-5 : @TEST4_LIB.\89EBPES12N3\(SCH_1):PAGE5 12_0V 3_3VAUX C_PCIE_3.3AUX 6C4< 3_3V 0.020 PMOSFET 22NF 0603 6800PF 0603 C_PCIE_12V 6D4< MIC2591B 23.2K IREF VAUXA 110K RFTR 12VINA 0.01UF CFTRA 0.01UF CFTRB 12VSNSA F_ONA* 12GATEA 3_3V F_ONB* GPI_A0 12VOUTA FORCE ON GPI_B0 3VINA AUXENA 0.013...
  • Page 37 CR-6 : @TEST4_LIB.\89EBPES12N3\(SCH_1):PAGE6 PLACE ALL CAPS NEAR PCIE CONNECTOR 3_3VC 3_3VC B_PCIE_3.3V 5A1> C_PCIE_3.3V 5C1> 12_0VC 12_0VC B_PCIE_12V 5B1> C_PCIE_12V 5D1> MOLEX64 MOLEX64 +12V PRSTN1# +12V PRSTN1# +12V +12V +12V +12V RSVD +12V RSVD +12V 3C5< E_SSMBCLK 7C7> 6C4< SMCLK...
  • Page 38 CR-7 : @TEST4_LIB.\89EBPES12N3\(SCH_1):PAGE7 3_3VAUX 12_0V 3_3V 3_3V 12_0V MOLEX_PCI_64_CONN +12V PRSTN1# 10UF C244 +12V +12V RSVD +12V 10UF 3C5< 9B8<> E_SSMBCLK SMCLK JTAG2 6C4< 4B7> 6C8< E_SSMBDATA SMDAT JTAG3 9B8<> 3C5< 6C4< 6C8< 4B7> JTAG4 10UF C243 +3.3V JTAG5 JTAG1 +3.3V...
  • Page 39 CR-8 : @TEST4_LIB.\89EBPES12N3\(SCH_1):PAGE8 1_5V 1_0VDDPE 3_3V 1_0VA VDDPE_J 3_3V_J JUMPERS MUST BE POPULATED FOR NORMAL OPERATION HDR_1X2_100 HDR_1X2_100 HDR_1X2_100 HDR_1X2_100 VDDCORE VDDCORE VDDCORE VDDCORE VDDCORE PES12N3 VDDCORE VDDCORE VDDCORE VDDAPE VTTPE VDDIO VDDCORE VDDAPE VTTPE VDDIO VDDCORE C218 VDDAPE VTTPE...
  • Page 40 CR-9 : @TEST4_LIB.\89EBPES12N3\(SCH_1):PAGE9 PES12N3 PES12N3 E_PEALREV 4B4> PEALREV E_REFCLK1P 3C1> PEREFCLKP2 U_PERP0 0.1UF U_PETP0 E_REFCLK1N 7C6> 7B3< 3C1> PEARP00 PEATP00 PEREFCLKN2 0402 E_REFCLK0P U_PERN0 0.1UF U_PETN0 7B6> 7B3< 3C1> PEARN00 PEATN00 PEREFCLKP1 U_PERP1 0.1UF 0402 U_PETP1 E_REFCLK0N 7B6> 7B3< 3C1>...
  • Page 41 CR-10 : @TEST4_LIB.\89EBPES12N3\(SCH_1):PAGE10 3_3VAUX 3_3VAUX 3_3V 3_3V 3_3V B_WAKE* 3_3V 6C8> 3_3V 3_3V PGOOD_B_N 5C8> 3C5< 4B1> SN74LVC1G125 TLC7733D RESINN HDR6 SENSE RESET CONTROL RESETN E_B_PERST* B_PERST* 9B5<> SN74LVC1G125 6C5< E_PERSTN 9D7< 3_3VAUX 3_3VAUX 10A5< C_WAKE* 6C4> U_WAKE* R131 7C6<...

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