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IDT Tsi620 User Manual

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IDT
Tsi620 Evaluation Board

User Manual

60D7000_MA001_03
August 7, 2009
6024 Silver Creek Valley Road San Jose, California 95138
Telephone: (408) 284-8200 • FAX: (408) 284-3572
Printed in U.S.A.
©2009 Integrated Device Technology, Inc.

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Summary of Contents for IDT Tsi620

  • Page 1: User Manual

     Tsi620 Evaluation Board User Manual 60D7000_MA001_03 August 7, 2009 6024 Silver Creek Valley Road San Jose, California 95138 Telephone: (408) 284-8200 • FAX: (408) 284-3572 Printed in U.S.A. ©2009 Integrated Device Technology, Inc.
  • Page 2 IDT does not assume responsibility for use of any circuitry described herein other than the circuitry embodied in an IDT product. Disclosure of the information herein does not convey a license or any other right, by implication or otherwise, in any patent, trademark, or other intellectual property right of IDT. IDT products may contain errata which can affect product performance to a minor or immaterial degree.

  • Page 3: Table Of Contents

    Running the FPGA Software ............48 Intergrated Device Technology Tsi620 Evaluation Board User Manual www.idt.com...
  • Page 4 PMC/DSP/FPGA Software Execution............53 Tsi620 Evaluation Board User Manual...

  • Page 5: About This Document

    About this Document This document discusses the functional characteristics of the Tsi620 evaluation board. It describes the board’s key specifications, system architecture, and hardware implementation approaches. In addition, it discusses the board’s configuration options, connectors, and LEDs. The next version of this document will explain how the board’s software can be used to test the board’s PMC, FPGA, and DSP capabilities.

  • Page 6: Revision History

    Revision History 60D7000_MA001_03, Formal, August 2009 There are no technical changes to this document. 60D7000_MA001_02, Formal, November 2008 This version was updated to include information about the software on the Tsi620 evaluation board (see “Board Software”). 60D7000_MA001_01, Preliminary, June 2008 This is the first version of the Tsi620 Evaluation Board Manual.

  • Page 7: Board Hardware

    To demonstrate the Tsi620’s potential application in a typical wireless baseband processing system • To provide a hardware platform for customers to assess the Tsi620’s major features and to evaluate the performance of the device in a real wireless base station system •...
  • Page 8 Tsi620 sRIO switch. Both upstream and downstream data flow can be implemented. The data transfer between the DSP and FPGA is through the Tsi620 using two 1x sRIO links so that the FPGA can function as a powerful accelerator to assist DSP baseband processing. The on-board PrPMC connector, which can function as the system management host and Ethernet networking interface, supports all standard PrPMC modules.

  • Page 9: Board Specification

    — Four OBSAI/CPRI links to the FPGA support OBSAI at 768 Mbps or CPRI at 614.4 Mbps — One GigE SGMII port to RJ45 connector — Dual x1 sRIO ports to Tsi620 sRIO switch with 5 Gb bandwidth • Altera Stratix3 FPGA —...
  • Page 10 1.2.2.3 sRIO Fabric • Tsi620 functions as the central hub to provide high-bandwidth data traffic of backplane, FPGA, DSP, and PrPMC • Tsi620 sRIO switch with dedicated PCI Interface and RIO XGMII port • 4x sRIO link to AMC-sRIO backplane with 10-Gb bandwidth •...

  • Page 11: Board Architecture

    3.3V@100mA for AMC management power 1.2.3 Board Architecture Figure 2 displays the architecture of the Tsi620 evaluation board. The board includes the following functional blocks; each block’s architectural features are discussed in the next section (see “Board Hardware Functional Description”): •...

  • Page 12: Board Hardware Functional Description

    DDR2 256MB RESET Control Board Hardware Functional Description 1.3.1 sRIO Switching and PrPMC Module Tsi620 sRIO switch provides the high-speed interconnection of AMC backplane, on-board vertical AMC slot, Stratix3 FPGA, TI DSP, and the processor module (see Figure 1.3.1.1 sRIO Switch •...
  • Page 13 01 = 2.5 Gb 00 = 1.25 Gb (S4 bit[4:3]) SP_CLK_SEL[1:0] 01 = 156.25 MHz SP(n)_PWRDN n=2,4,5,6 0 = Port 2, 4, 5, 6 are powered up (assuming SP(0) is always powered up) Intergrated Device Technology Tsi620 Evaluation Board User Manual www.idt.com 60D7000_MA001_03...
  • Page 14 — Tsi620 internal PCI arbiter — Tsi620 PCI clock generator performs PCI clocking — PCI interrupt handler: PrPMC module — Tsi620 drives reset to PrPMC (PrPMC may issue system reset from PMC_RESETOUT#) • PrPMC: system host for sRIO switching and monarch for PCI bus •...
  • Page 15 0 = PCI PLL is enabled PCI_ARBEN 1 = PCI internal arbiter is used PCI_HOLD_BOOT 0 = Release PCI software reset immediately after a Tsi620 reset is completed SPARE[1:0] 00 = Tsi620 (pull-up/down required for BOM selection) Table 3: PrPMC Interrupt Routing...
  • Page 16 • Mini USB connector on front panel with USB2.0 compatible • Tsi620 GPIO[0:15] connection to DSP and FPGA • Standard JTAG header for Tsi620 on-die scope support Table 4: I2C Power-Up Configuration Setting Pin Name Setting Description I2C_MA (PU) 1 = Multi-byte peripheral addressing...

  • Page 17: Fpga Block

    Mictor RX_CLK XGMII Tx 38pin XGMII Rx 38pin Switching Tsi620 Fabric GPIO[0:15] Stratix3 FPGA FSYNC_OUT 780FBGA FSYNC_IN SMT_IN Header EPCS64 AS-CFG EMAC GigE_REF(p,n) x8/10 10/100M 156.25MHz 30.72MHz_REF 100BaseT JTAG RJ45 Intergrated Device Technology Tsi620 Evaluation Board User Manual www.idt.com 60D7000_MA001_03...
  • Page 18 Up to 12-Gb bandwidth of data transfer between FPGA and sRIO switch • Reference clock: RX_CLK from Tsi620 • Frequency: 62.5, 125, or 156.25 MHz (Note: Revision 1 of the Tsi620 evaluation board does not support 156.25 MHz. • Tx_CLK: sync with Rx-CLK and must be PLL locked before driving out •...

  • Page 19: Dsp Block

    Boot mode: I2C, EMAC, sRIO • 16-bit GPIO assignment: — 4 bits to FPGA — 4 bits to Tsi620 through AFS600 — 1 bit to PrPMC for interrupt — 1 bit to AFS600 for status report — 6 bits for DSP local configuration •...
  • Page 20 FPGA link: 4x to FPGA with up to 768 Mbps per lane • CPRI compatible: 614.4 Mbps, 1.2288 Gbps, 2.4576 Gbps link rates • OBSAI compatible: 768 Mbps, 1.536 Gbps, 3.072 Gbps link rates Tsi620 Evaluation Board User Manual Intergrated Device Technology 60D7000_MA001_03 www.idt.com...
  • Page 21 Interrupts between DSP and FPGA through DSP_GPIO[12:15] with active low • Interrupts between DSP and Tsi620 by DSP_GPIO[6] through the AFS600 as the level shift. Note: Care must be taken that the interrupt signals must be always driven after the reset once their direction and function has been defined.

  • Page 22: System Management Controller

    • UART port to USB interface • Board status report For more information on the function of the system controller, see the source files for the Tsi620 Evaluation Board System Controller (35D7000_PL007). Figure 6: System Management Controller 3.3V_MP 1.5V 1.5V_Reg...

  • Page 23: Reset Control

    FPGA soft reset and no affect to PLL V8221 HRESETn 3.3VLVTTL GigE PHY reset Reset Control Logic • System management controller: Actel AFS256-FG256, Flash-based mixed signal FPGA • Supports multi-volt device control Intergrated Device Technology Tsi620 Evaluation Board User Manual www.idt.com 60D7000_MA001_03...

  • Page 24: Clocking Management

    AFS600-FG256 Fusion mixed-signal FPGA, and is supported by IPMI firmware from uBlade. The MMC design supports the basic requirements defined by the PICMIG AMC.0 and Intel IPMI v2.0 specifications. For additional information about the MMC design, contact the Actel or IDT Technical Support team.
  • Page 25 Table 7 summarizes the clocking sources requirements for all major components on the Tsi620 evaluation board. Table 7: Clocking Sources List Clock Name Function/Domain Logic Standard Frequency Input Jitter SCLK(p,n) Tsi620 system LVDS/PECL(AC) 156.25 MHz reference SP6_RXCLK Tsi620 XGMAI RXCLK HSTL-1.5V...

  • Page 26: Power Management

    The Tsi620 FMAC and FPGA RIO-XGMII interface function in the synchronous mode. The TX_CLK from the Tsi620 is sourcing from its SYSCLK(p,n), while the FPGA must use RX_CLK as its RIO-XGMII operation reference clock. The TX_CLK driven from the FPGA must therefore be synchronized with TX_CLK driven by the Tsi620.
  • Page 27 The LTM4604, 4A, (15 mm x 9 mm x 2.3 mm) DC/DC switching regulator generates +1.2V, +1.5V, +1.8V, and +2.5v from either 5V rail or 3.3V rail. • -12V is implemented on-board for PrPMC only with max I <= 350mA Intergrated Device Technology Tsi620 Evaluation Board User Manual www.idt.com 60D7000_MA001_03...
  • Page 28 Assuming the power consumption of DSP + DDR2 are <10W • Assuming the power consumption of MISC is <10W • Assuming the power consumption of Tsi620 is <5W So, the maximum power consumption allowed for the AMC vertical slot is <15W. Tsi620 Evaluation Board User Manual Intergrated Device Technology 60D7000_MA001_03 www.idt.com...

  • Page 29: Jtag Port And I2C Bus

    The Altera FPGA and Actel FPGA are in the same 3.3V JTAG chain (they share the single 10-pin JTAG header) • Tsi620’s internal registers can be accessed by either USB or JTAG header Intergrated Device Technology Tsi620 Evaluation Board User Manual www.idt.com...

  • Page 30: Pcb Characteristics

    • The FDTI-2232D is self-powered by 3.3V_USB from the mini-USB connector. It provides bridges the USB interface and JTAG port for the Tsi620, and also provides a USB to UART interface for the AFS600. • JTAG connectors for the following: —...

  • Page 31: Configuration Options

    Configuration Options This section describes the configuration options for the Tsi620 evaluation board. 1.5.1 DIP Switches Switches S1 to S5 combine four small slide switches identified with numbers 1 to 4 (see example in Figure 5). For information on the individual DIP switches, see Tables 9 to 13.
  • Page 32 CFG2 - 1.25 G (Default) OFF-OFF-ON-OFF 1-1-0-1 sRIO Boot – 3.125 G CFG3 – 3.125 G All others Reserved 1.5.1.2 S2 – Tsi620 GPIO Setting Table 10: S2[1:2:3:4] Setting Switch S2 Signal Assignment Default ON/OFF Setting Bit 1 Tsi620_GPIO16 ON = 0 or logic low...
  • Page 33 ON = 0 or logic low to FPGA OFF = 1 or logic High to FPGA Bit 4 AFS_SET_3V3 1 = OFF Reserved 1.5.1.4 S4 – Tsi620 Option Setting Table 12: S4[1:2:3:4] Setting Switch S4 Signal Assignment Default ON/OFF Setting Bit 1...

  • Page 34: Jumpers

    1.5.2 Jumpers The Tsi620 evaluation board has only one jumper, J6, which is reserved for the future use. This jumper should be left open for the normal operation. 1.5.3 Push Button and Toggle Switch Reference Designator Switch Type Signal Assignment...
  • Page 35 Figure 11: Location of Switches and Connections AMC-GigE DSP-GigE Intergrated Device Technology Tsi620 Evaluation Board User Manual www.idt.com 60D7000_MA001_03...

  • Page 36: Board Connectors

    Actel FPGA without consulting the IDT Technical Support team. b. Both J10 and U35 can be used to access the Tsi620’s internal registers through its JTAG port; however, they work exclusively. c. FT2232D has independent USB-to-JTAG and USB-to-UART channels.

  • Page 37: Sma Connectors

    A 32-pin Mictor connector attached to the FPGA PrPMC J17, J18, Standard PrPMC card connector a. IDT recommends minimal 5A supply capability. LEDs and Display The following figure shows the location of the board’s LEDs and displays. Intergrated Device Technology Tsi620 Evaluation Board User Manual www.idt.com...
  • Page 38 Figure 12: Location of LEDs and Displays (Top View) Tsi620 Evaluation Board User Manual Intergrated Device Technology 60D7000_MA001_03 www.idt.com...

  • Page 39: Power Good Indicators

    Orange Indicates 5V is good Orange Indicates 3.3V is good Green Indicates 1.1V_DSP is good Green Indicates 1.1V_FPGA is good a. Not supported by the Tsi620 evaluation board. 1.7.2 AMC MMC LEDs Reference Designator Color Description Yellow Pharos Flash: Normal operation...

  • Page 40: Sfp Optical Transceiver Leds

    1 = OFF Yellow Tsi620 GPIO21: 0 = ON 1 = OFF Yellow Tsi620 GPIO22 0 = ON 1 = OFF Yellow Tsi620 GPIO23 0 = ON 1 = OFF Tsi620 Evaluation Board User Manual Intergrated Device Technology 60D7000_MA001_03 www.idt.com...

  • Page 41: Board Software

    Linux kernel into PCI accesses that perform the requested operations from the Tsi620. While the source code for this driver is available on the companion CD for the Tsi620 evaluation board, the driver is not licensed under the GPL and should not be compiled into the kernel. As a result, only the compiled binary kernel module (tsi620.ko) should be distributed to customers (for licensing information, please...

  • Page 42: Running The Software Using Ramdisk

    RapidIO system being enumerated, this driver must be loaded after the RapidIO hardware driver. As the Tsi620 driver may only be loaded from a binary module after boot, the device access driver should also be compiled as a binary module and loaded after the Tsi620 driver. This driver may be released under the GPL, and the source code is included with the Linux kernel code on the companion CD for Tsi620 evaluation board.

  • Page 43: Running The Software Using Nfs Server

    6. Load the binary kernel drivers by executing insmod ./tsi620.ko followed by insmod ./rio-dev.ko. 7. Enter the command ls to see a list of directory contents. There are two programs: • askdsp • memdump 8. Enter the command ./memdump to see the contents of a portion of the DSP L2 cache. Additional areas of DSP memory space can be viewed by specifying the memory address.

  • Page 44: Installing The Pmc Software

    ELDK 4.1 software available from DENX (www.denx.de) with the “ARCH” and “CROSS_COMPILE” environment variables set to “powerpc” and “ppc_82xx-” respectively. Note that the included Linux kernel source has been modified by IDT to support additional RapidIO functionality, and to include the rio-dev driver. These modifications can be distributed to customers or applied to your own custom software under the terms of the GPL.

  • Page 45: Fpga Software

    2.1.4.2 Modifying the Tsi620 Driver The Tsi620 low-level driver is not included in the Linux kernel source code because it is not licensed under the GPL. To compile the binary kernel module, first compile the kernel as described above. Uncompress the Tsi620 driver into a location of your choice and — from the Linux kernel source directory —...

  • Page 46: Installing The Fpga Software

    Next, launch the a NIOS II Command Shell by selecting START->All Programs->Altera->NIOS II EDS 7.2->NIOS II 7.2 Command Shell. This should create a window like the one shown in Figure Figure 13: NIOS II Command Shell Window Tsi620 Evaluation Board User Manual Intergrated Device Technology 60D7000_MA001_03 www.idt.com...
  • Page 47 2. Under the File menu, select Import. An Import dialog window will pop up. 3. In the Import dialog window, select “Existing NIOS II software build tools project or folder into workspace”. Intergrated Device Technology Tsi620 Evaluation Board User Manual www.idt.com 60D7000_MA001_03...

  • Page 48: Running The Fpga Software

    5. Navigate to the directory that contains the hardware configuration you want to execute, then select the file named “srio_1250_x4.sof”. The “.sof” indicates that this is an FPGA hardware configuration file. Other hardware configurations have similarly named files, all ending in “.sof”. Tsi620 Evaluation Board User Manual Intergrated Device Technology 60D7000_MA001_03 www.idt.com...

  • Page 49: Fpga Hardware Load Facilities

    . The processor can access RX_MEMORY starting at address 0x80000. 1. For more information on the RapidIO Avalon Master or Slave, see the RapidIO MegaCore Function User Guide available at www.altera.com. Intergrated Device Technology Tsi620 Evaluation Board User Manual www.idt.com 60D7000_MA001_03...

  • Page 50: Software Environment

    2. MNIT and MEM commands – To initialize and display the TX_MEMORY and RX_MEMORY 3. GET and LOAD commands – To read and write hardware registers and memory 4. RMR and RMW commands – To verify RapidIO connectivity to the Tsi620 and other RapidIO devices.

  • Page 51: Dsp Software

    Blackhawk emulator to physically transfer data from CCS to the DSP hardware (for information on ordering a Blackhawk emulator, see www.blackhawk-dsp.com). IDT recommends the purchase of the Blackhawk “Bus-powered USB560 JTAG emulator” product. This emulator requires a 14-pin to 60-pin converter module from Blackhawk, model number BH-14e_TI-60t_TI.

  • Page 52: Running The Dsp Software

    2. Select “File->Import” and browse to the Tsi620EVB.ccs file found on the CD in the “DSP” directory. This configures CCS and the Blackhawk emulator to use the 3-core DSP mounted on the Tsi620 evaluation board. 3. Click “Save and Quit” and launch Code Composer Studio.

  • Page 53: Pmc/Dsp/Fpga Software Execution

    To execute the PMC software at the same time as the DSP and FPGA software, the following order of software execution must be used: 1. After the Tsi620 evaluation board is powered up, the DSP and FPGA software must be started before the PMC software can be started.
  • Page 54 Tsi620 Evaluation Board User Manual Intergrated Device Technology 60D7000_MA001_03 www.idt.com...
  • Page 55 CORPORATE HEADQUARTERS for SALES: for Tech Support: 6024 Silver Creek Valley Road 800-345-7015 or 408-284-8200 408-360-1533 San Jose, CA 95138 fax: 408-284-2775 sRIO@idt.com www.idt.com Document: 60D7000_MA001_03 August 7, 2009...

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