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WAN PLL
INTRODUCTION
The 82V3911 evaluation board kit, including an evaluation board and
evaluation software, provides a platform to evaluate 82V3911.
The evaluation board kit contains the following components:
• 82V3911 evaluation board ver 1.00 with all necessary components
• 82V3911 evaluation GUI software ver 1.00
• 82V3911 evaluation board user's guide ver 1.0
FEATURES
• Professional evaluation software to configure and monitor the device
• Current configuration data can be saved as a file for later use
82V3911 REVISION 1 1/30/15
EVALUATION BOARD USER'S GUIDE
PC REQUIREMENTS
The 82V3911 evaluation software runs on Microsoft Windows. The
system requirements are as follows:
• Pentium 166 MMX or higher (recommended)
• Minimum 500M bytes free hard disk space
• Minimum 64M bytes memory
• Display with the resolution of 1024x768, small font (recommended)
• Operating System: Microsoft Windows 2000/XP/NT (English version
recommended) or newer OS version
• Microsoft Windows compatible 2-button or 3-button mouse
1
82V3911
©2014 Integrated Device Technology, Inc.
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Summary of Contents for IDT 82V3911
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Page 1: Introduction
82V3911 EVALUATION BOARD USER’S GUIDE INTRODUCTION PC REQUIREMENTS The 82V3911 evaluation board kit, including an evaluation board and The 82V3911 evaluation software runs on Microsoft Windows. The evaluation software, provides a platform to evaluate 82V3911. system requirements are as follows: •... -
Page 2: Table Of Contents
82V3911 WAN PLL TABLE OF CONTENTS INTRODUCTION ..................................1 FEATURES ....................................1 PC REQUIREMENTS................................1 HARDWARE CONFIGURATION ............................3 ANNOTATION FOR FIGURE-1 ..........................4 SOFTWARE CONFIGURATION .............................5 INSTALLATION ..............................5 GENERAL INTRODUCTION ..........................5 2.2.1 Overview..............................5 2.2.2 Conventions used...........................5 2.2.3 DPLL1/ DPLL2 Path Selection .......................6 2.2.4... -
Page 3: Hardware Configuration
82V3911 WAN PLL HARDWARE CONFIGURATION Figure-1 82V3911 Evaluation Board Illustration REVISION 1 1/30/15 EVALUATION BOARD USER’S GUIDE... -
Page 4: Annotation For Figure-1
82V3911 WAN PLL ANNOTATION FOR FIGURE-1 [1] Output clock 1 - 5 [4] Crystal oscillator Master Clock [2] 82V3911 chip [5] +5 V DC power supply [3] Switch SW5: The function of this switch is described in [6] +3.3 V power supply for test purpose Table-1. -
Page 5: Software Configuration
2.2.1 OVERVIEW The 82V3911 evaluation software provides a friendly interface for users Name Image (Example) Convention Used to configure and control the 82V3911. As shown in Figure-2, the main window includes: “Window > Monitor” menu bar Menu bar Shortcut icon ... -
Page 6: Dpll1/ Dpll2 Path Selection
82V3911 WAN PLL input ports configuration DPLL1 & DPLL2 path configuration output ports configuration menu bar shortcut icons main work area general configuration status bar DPLL1/ DPLL2 path selection DPLL status indication Figure-2 Graphic User Interface (GUI) 2.2.3 DPLL1/ DPLL2 PATH SELECTION 2.2.4... -
Page 7: Tips For The Parameters And Buttons
82V3911 WAN PLL 2.2.6 TIPS FOR THE PARAMETERS AND BUTTONS View Menu The evaluation software provides tips for the parameters, shortcut icons and buttons to help users make configurations. For example, when the toggle the shortcut icons mouse focus is on a parameter, a tip will appear displaying the related toggle the status bar register’s name, address and bits. -
Page 8: Shortcut Icons
82V3911 WAN PLL Window Menu 2.2.8 SHORTCUT ICONS The Window menu contains 13 sub-menus as shown in Figure-9. All The functions of the shortcut icons are described in the following table: these sub-menus except “Register Set II” and “Hide All Popup” have the... -
Page 9: Initialization
The evaluation software will automatically select the port which successfully communicates with click to extend the input ports the 82V3911 evaluation board. frequency selection configuration Click on “OK”, and the evaluation board will be initialized and the interface main window will appear as shown in Figure-2. - Page 10 82V3911 WAN PLL allow/dis-allow lock to the input clock (checked: allow) leaky bucket configuration selection lock 8k divider (checked: used) input clock quality indication (checked: valid) DivN divider (checked: used) hard frequency alarm indication (checked: has alarm) priority setting no activity indication (checked: no activity)
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Page 11: Leaky Bucket Configuration
82V3911 WAN PLL 2.4.1 LEAKY BUCKET CONFIGURATION Click on “Buckets” or select “Window > Bucket Window”. The buckets dialog box pops up as shown in Figure-15. Users can set the four leaky bucket configurations in this dialog box. configuration 1... -
Page 12: Monitor Configuration
82V3911 WAN PLL MONITOR CONFIGURATION Click on “Monitor” or select “Window > Monitor”. The Monitors dialog box pops up as shown in Figure-17. In this dialog box, users can configure the input clock quality monitor. register address and bits hard frequency alarm configuration... -
Page 13: Dpll2 Path Configuration
82V3911 WAN PLL DPLL2 PATH CONFIGURATION 2.6.2 DPLL2 DPLL Click on “DPLL2 PFD & LP” or select “Window > DPLL2”. The DPLL2 2.6.1 DPLL2 INPUT SELECTOR dialog box pops out as shown in Figure-19. This dialog box allows users to Click on “DPLL2 Input Selector”... -
Page 14: Dpll2 Dco Output Clock Frequency Selection
82V3911 WAN PLL 2.6.3 DPLL2 DCO OUTPUT CLOCK FREQUENCY SELECTION 2.6.4 DPLL2 SONET/GETH CONFIGURATION Click on “GSM/GPS/16E1/16T1”, “16E1/16T1” and “12E1/24T1/E3/T3” Click on “SONET/GETH” to select an input source for the DPLL2 in the DPLL2 path to select the DCO output clock frequency. See Figure- SONET/GETH. -
Page 15: Dpll1 Path Configuration
82V3911 WAN PLL DPLL1 PATH CONFIGURATION 2.7.1 DPLL1 INPUT SELECTOR Click on “DPLL1 Input Selector” or select “Window > DPLL1 Input”. The following dialog box pops out, allowing users to select an input for the DPLL1. DPLL1 Auto/Forced input clock selection... -
Page 16: Hs And Phase Offset Configuration
82V3911 WAN PLL 2.7.3 HS AND PHASE OFFSET CONFIGURATION Click on “HS & Offset” or select “Window > HS Phase Offset”. The HS and Phase Offset dialog box pops out as shown in Figure-24. This dialog box allows users to configure HS & phase offset. -
Page 17: Output Ports Configuration
82V3911 WAN PLL OUTPUT PORTS CONFIGURATION The default output ports configuration interface is as shown in Figure- division factor selection of the output clock 27. Click on “<< More”, and this interface extends to show all output- related configuration information. See Figure-28 for details. -
Page 18: Ethernet Clock Configuration For Output Ports
82V3911 WAN PLL 2.8.1 ETHERNET CLOCK CONFIGURATION FOR OUTPUT PORTS Following is an example using Ethernet clocks from the DPLL1 SONET/GETH (625 MHz) path to configure the output 6. The steps below are performed from the main GUI (refer to Figure-2). -
Page 19: Frame And Multi-Frame Configuration
82V3911 WAN PLL 2.8.2 FRAME AND MULTI-FRAME CONFIGURATION Click on “SYNC” or select “Window > Output Frame Sync”. The Frame and Multi-Frame configuration dialog box pops up as shown in Figure-32. checked: 2 kHz/4 kHz/8 kHz register address and bits input clock inverted FRSYNC_8K &... -
Page 20: Other Configuration
82V3911 WAN PLL OTHER CONFIGURATION 2.9.1 REGISTERS CONFIGURATION Register Set I Dialog Box Click on “MPU Interface and Registers” or select “Window > Register Set I”. The Register Set dialog box pops up as shown in Figure-33. Users can configure all registers or check the status of all registers in this dialog box. -
Page 21: Interrupts Configuration
82V3911 WAN PLL 2.9.2 INTERRUPTS CONFIGURATION Click on “Interrupt” or select “Window > Interrupt Window”. The Interrupt dialog box pops up as shown in Figure-35. register bit (interrupt name) register address interrupt enable/disable (checked: enable) interrupt source status indication (red: status changed; green: status not changed) -
Page 22: 2.10 Dpll Status Indication
82V3911 WAN PLL 2.10 DPLL STATUS INDICATION The DPLL status indication area is as shown in Figure-36. Users can choose to show DPLL1 or DPLL2 status. Here shows the situation that DPLL1 is selected. valid input clock currently selected valid input clock... - Page 23 82V3911 WAN PLL Right click the graphic area Printing the displayed graphics Refreshing data display Setting the graphic properties Figure-38 Context Menu Items Show/hide the grid lines Show/hide the scale numbers on Check this item to prevent graphic flicker the right side of the diagram...
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Page 24: 2.11 Page 1 Registers Configuration
82V3911 WAN PLL 2.11 PAGE 1 REGISTERS CONFIGURATION Click the button of Page 1 Registers Access in the main window, the user can configure the registers in the page 1. See Figure-40 for details. Click on the button, then select the DFS enable... -
Page 25: Appendix: Schematic File
82V3911 WAN PLL APPENDIX: SCHEMATIC FILE REVISION 1 1/30/15 EVALUATION BOARD USER’S GUIDE... - Page 26 82V3911 WAN PLL 966$ 966$ 966$2 966$2 &$3 & 966$2 &$3 966$2 &$3 966$2 966$2 9''$ 966$2 9''$ 966$2 9''$ 966$2 9''$ 966$2 9''$ & 966$2 9''$ 966$2 9''$ 966$2 9''$ 966$2 966$2 9''' 966$2 9''' 966$2 9''' 966$2 9'''...
- Page 27 82V3911 WAN PLL 287 287 287 Q287 287 287 287 Q287 287 287 287 Q287 )5B. 287 )5B. Q287 REVISION 1 1/30/15 EVALUATION BOARD USER’S GUIDE...
- Page 28 82V3911 WAN PLL 1& 1& '1& 7ULVWDWHB(QDEOH 1& 1& '1& 1& $9&& $*1' 9&& 9&& 9&&,2$ 9&&,2% REVISION 1 1/30/15 EVALUATION BOARD USER’S GUIDE...
- Page 29 82V3911 WAN PLL H3$' H3$' REVISION 1 1/30/15 EVALUATION BOARD USER’S GUIDE...
- Page 30 IDT or any third parties. IDT’s products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users.
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