Input And Output Circuits - IAI CV-M40 Operating Manual

5.3. Input and Output Circuits

In the following schematic diagrams the input and output circuits for video and timing signals
are shown.
Video output
The video output is a 75 Ω DC coupled
circuit. The video DC level for video and
video + sync is shown with 75 Ω
termination.
The vertical composite sync is with
serration and equalize pulses.
HD, VD and Trigger input
The inputs are AC coupled. To allow
longer pulse width, the input circuit is
a flip flop, which is toggled by the
negative or positive differentiated spikes
caused by the falling and rising edge.
The input is TTL as factory setting.
It can be 75Ω terminated by jumper.
As factory setting HD and VD are input.
Warning! In trigger modes, the HD and VD
input circuits are used as trigger inputs.
Do not connect signal not used for the
actual trigger mode.
HD, VD, WEN and PCLK output
Output circuit for HD, VD, WEN and pixel clock
is TTL through emitter follower with 75 Ω in series.
Output level ≥4 V from 75Ω. (Non-terminated).
WEN active polarity is positive 1H. It can be changed
to be active low. The WEN timing then depend of
the actual mode. Refer to timing diagrams.
If not used, the pixel clock should be disabled.
CV-M40
CXA CXA
1310 1310
Fig. 4. Video output.
HD VD HD VD
Trigger Trigger
input input
Fig. 5. HD, VD and Trigger input.
Fig. 6. HD, VD, WEN and PCLK output.
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#4/12 #4/12
Video Video
Output Output
75 75 FL FL
BNC BNC
GND GND
33k 33k
100n 100n 1k 1k
33k 33k
100k 100k
JP JP
75 75
1n 1n
10k 10k
TTL TTL
220 220
10 10
10 10
10k 10k
DC level with DC level with
75 Ω termination 75 Ω termination
300 mV 300 mV
470 mV 470 mV
+5V +5V
TTL TTL
1k 1k
GND GND
67 67
GND GND