VersaLogic SandCat Programmer's Reference Manual page 27

TEMPICR – Temperature Interrupt Control Register
This is the interrupt mask register for the temperature sensor thermal alerts and the DDR3
SODIMM EVENT signals and the interrupt enable and selection. The SODIMM may not have
any temperature event capability. Reset type is Platform.
Table 26: TEMPICR – Temperature Interrupt Control Register
Bits Identifier
7 IRQEN
6-4 IRQSEL(2:0)
3 IMASK_BATTLOW
2 IMASK_EVENT
1 IMASK_THERM
0 IMASK_ALERT
TEMPISTAT – Temperature Interrupt Status Register
Reset type: n/a.
Table 27: TEMPISTAT – Temperature Interrupt Status Register
Bits Identifier
7
Reserved
6-4 Reserved
3
Reserved
2 ISTAT_EVENT
1 ISTAT_THERM
0 ISTAT_ALERT
EPM-39 Programmer's Reference Manual
Access Default
Temperature interrupt enable/disable:
R/W
0 0 – Interrupts disabled
1 – Interrupts enabled
Temperature interrupt IRQ select in LPC SERIRQ:
000 – IRQ3
001 – IRQ4
010 – IRQ5
R/W
000
011 – IRQ10
100 – IRQ6
101 – IRQ7
110 – IRQ9
111 – IRQ11
Battery-low interrupt mask:
R/W
0 0 – Interrupt disabled
1 – Interrupt enabled.
SODIMM EVENT output interrupt mask:
R/W
0 0 – Interrupt disabled
1 – Interrupt enabled.
Temperature Sensor THERM output interrupt mask:
R/W
0 0 – Interrupt disabled
1 – Interrupt enabled.
Temperature Sensor ALERT output interrupt mask:
R/W
0 0 – Interrupt disabled
1 – Interrupt enabled.
Access Default
RO
RO
000 Reserved. Writes are ignored; reads always return 0.
RW/C
SODIMM EVENT interrupt status. A read returns the interrupt
RW/C
N/A
status. Writing a '1' will clear the interrupt status
Temperature Sensor THERM interrupt status. A read returns the
RW/C
N/A
interrupt status. Writing a '1' clears the interrupt status
Temperature Sensor ALERT interrupt status. A read returns the
RW/C
N/A
interrupt status. Writing a '1' clears the interrupt status
FPGA Registers
Description
Description
22