Double Buffering; Ed/Hd Doubling Buffering; Sd Doubling Buffering - Analog Devices ADV8005 Hardware Reference Manual

UG-707
Setup Level (NTSC) with Pedestal
22.5 IRE
15 IRE
7.5 IRE
0 IRE
1 Values in the range of 0x3F to 0x44 may result in an invalid output signal.
7.4.15.

Double Buffering

Double buffered registers are updated once per field. Double buffering improves overall performance because modifications to register settings
are not made during active video but take effect prior to the start of the active video on the next field. This can be enabled for both SD and
ED/HD using db_en and db_en_hdtv
7.4.15.1.

ED/HD Doubling Buffering

db_en_hdtv, Encoder Map, Address 0xE433[7]
This bit is used to enable the double buffering on the appropriate ED/HD registers.
Function
db_en_hdtv
0 (default)
1
Double buffering can be activated on the following ED/HD functions: the ED/HD gamma A and gamma B curves and the ED/HD CGMS
registers.
7.4.15.2.

SD Doubling Buffering

db_en, Encoder Map, Address 0xE488[2]
This bit is used to enable double buffering on the appropriate SD registers.
Function
db_en
1
0 (default)
Double buffering can be activated on the following SD functions: the SD gamma A and gamma B curves, SD Y scale, SD Cr scale, SD Cb scale,
SD brightness, SD closed captioning, and SD Macrovision bits (Reg 0xE4E0, Bits [5:0]).
Table 76: Sample Brightness Control Values
Setup Level (NTSC) Without Pedestal
15 IRE
7.5 IRE
0 IRE
−7.5 IRE
NTSC WITHOUT PEDESTAL
100 IRE
0 IRE
NO SETUP
VALUE ADDED
Figure 118: Examples of Brightness Control Values
respectively.
Description
Cb after falling edge of HSYNC
Cr after falling edge of HSYNC
Description
Enabled
Disabled
Rev. A | Page 260 of 317
ADV8005 Hardware Reference Manual
1
Setup Level (PAL)
15 IRE
7.5 IRE
0 IRE
−7.5 IRE
POSITIVE SETUP NEGATIVE SETUP
VALUE ADDED VALUE ADDED
Brightness Control Value
setup[6:0]
( )
0x1E
0x0F
0x00
0x71
+7.5 IRE
–7.5 IRE