Analog Devices ADV8005 Hardware Reference Manual page 8

UG-707
7.4.19. SD Digital Noise Reduction .............................................................................................................................................. 271
7.4.19.1. Coring Gain Border ....................................................................................................................................................................... 272
7.4.19.2. Coring Gain Data ........................................................................................................................................................................... 272
7.4.19.3. DNR Threshold ............................................................................................................................................................................... 273
7.4.19.4. Border Area ..................................................................................................................................................................................... 273
7.4.19.5. Block Size Control .......................................................................................................................................................................... 273
7.4.19.6. DNR Input Select Control ............................................................................................................................................................. 274
7.4.19.7. DNR Mode Control ........................................................................................................................................................................ 274
7.4.19.8. DNR Block Offset Control ............................................................................................................................................................ 275
7.4.19.9. SD Active Video Edge Control ..................................................................................................................................................... 275
7.5. Vertical Blanking Interval.............................................................................................................................................. 276
7.6. DAC Configurations ...................................................................................................................................................... 277
7.6.1. Voltage Reference ................................................................................................................................................................ 277
7.6.2. Video Output Buffer and Optional Output Filter .......................................................................................................... 277
8. Interrupts ................................................................................................................................................................. 280
8.1. Interrupt Pins .................................................................................................................................................................. 280
8.1.1. Interrupt Duration .............................................................................................................................................................. 280
8.1.2. Storing Masked Interrupts ................................................................................................................................................. 281
8.2. Serial Video Rx Interrupts ............................................................................................................................................. 281
8.2.1. Introduction ........................................................................................................................................................................ 281
8.2.2. Interrupt Architecture Overview ...................................................................................................................................... 284
8.2.2.1. Multiple Interrupt Events .................................................................................................................................................................... 285
8.2.3. Serial Video Interrupts Validity Checking Process ........................................................................................................ 285
8.3. VSP and OSD Section .................................................................................................................................................... 285
8.3.1. Interrupt Architecture Overview ...................................................................................................................................... 286
8.4. HDMI Tx core................................................................................................................................................................. 286
8.4.1. Introduction ........................................................................................................................................................................ 286
8.4.2. Interrupt Architecture Overview ...................................................................................................................................... 287
8.4.3. HDMI Tx Interrupt Polarity ............................................................................................................................................. 287
Appendix A ....................................................................................................................................................................... 288
PCB Layout Recommendations.................................................................................................................................................... 288
Analogue/Digital Video Interface Outputs ...................................................................................................................................... 288
External DDR2 Memory Requirements ........................................................................................................................................... 288
Power Supply Bypassing ..................................................................................................................................................................... 289
General Digital Inputs and Outputs ................................................................................................................................................. 289
XTAL and Load Cap Value Selection ................................................................................................................................................ 289
Encoder Component Placement ....................................................................................................................................................... 290
HDMI Transmitter Component Placement ..................................................................................................................................... 290
Power Supply Design and Sequencing .............................................................................................................................................. 290
Appendix B ........................................................................................................................................................................ 292
Unused Pin List .............................................................................................................................................................................. 292
Appendix C ....................................................................................................................................................................... 304
Pixel Input and Output Formats................................................................................................................................................... 304
ADV8005 Hardware Reference Manual
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