Side By Side Full; External Sync Mode - Analog Devices ADV8005 Hardware Reference Manual

UG-707
The following standards are NOT supported.
VI Format Int/Pr
C og
63 1920x10 Prog 119,88/
80p
64
1920x10 Prog
80p
3.5.5. 3D Side by Side Full
The following 3D standards need to go through the HPS before being converted to a 2D mode.
VI Format Int/Pr
C og
63 1920x10 Prog 119,88/
80p
64 1920x10 Prog
80p

3.6. EXTERNAL SYNC MODE

Using the ADV8005 external sync mode, it is possible to resynchronise multiple
outputs from multiple ADV8005
When the ADV8005 is in external sync mode, the output video timing will be locked to an externally provided master sync signal (MAS_VS).
This master signal must be provided to the MAS_VS ball. The polarity of this sync signal is assumed to be active high and will default to this
operation. mas_vs_ie, mas_hs_ie,
Assumptions for operating in this mode:
•
The external sync provided to the
supported, that is, extra or fewer pixels, lines or frames than specified in the standard. Note that the VS and HS are assumed to be
active high.
•
The sync signals supported will be VS and HS. Note that HS is optional and only required if interlaced output is required. In this case
the HS position with respect to the VS will be used to determine the output field required. If only progressive outputs are required then
the HS may be omitted and VS alone will suffice to lock the output.
•
The external timing provided should match the output video standard programmed. For example if 1080i60Hz is to be output from
the ADV8005 PVSP and locked to external timing then a 60 Hz Vsync signal should be provided on the MAS_VS pin and a
33.750 kHz HSync should be provided on the MAS_HS pin. In this case the
Field Pix H V
Rate el Fre Fre
[Hz] Fre q q
q [kH [Hz
[MH z] ]
z]
594 270 12
120 0
100 594 225 10
0
Field Pix H V
Rate el Fre Fre
[Hz] Fre q q
q [kH [Hz
[MH z] ]
z]
297 135 12
120 0
100 297 112 10
.5 0
devices will be locked to +/- 3 Xtal clock cycles, where the Xtal clock will be 27 MHz.
and mas_clk_ie are used to enable the respective external sync pins.
ADV8005
ADV8005 Hardware Reference Manual
H H H H
tota acti bla Fro
l ve nk nt
[dot [dot [dot Por
s] s] s] ch
[dot
s]
220 192 280 88
0 0
264 192 720 528
0 0
H H H H
tota acti bla Fro
l ve nk nt
[dot [dot [dot Por
s] s] s] ch
[dot
s]
220 192 280 88
0 0
264 192 720 528
0 0
ADV8005
will be a CEA-861 or VESA compliant VSync. Non standard timing will NOT be
Rev. A | Page 162 of 317
Hsy H V V
nc Bac total acti
[dot k [line ve
s] Por s] [line
ch s]
[dot
s]
44 148 225 220
0 5
44 148 225 220
0 5
Hsy H V V
nc Bac total acti
[dot k [line ve
s] Por s] [line
ch s]
[dot
s]
44 148 112 108
5 0
44 148 112 108
5 0
output video streams to an external sync input. The
pvsp_autocfg_output_vid[7:0]
V V Vsy V
blan Fro nc Bac
k nt [line k
[line Por s] Por
s] ch ch
[line [line
s] s]
45 4 5 36
45 4 5 36
V V Vsy V
blan Fro nc Bac
k nt [line k
[line Por s] Por
s] ch ch
[line [line
s] s]
45 4 5 36
45 4 5 36
should be set to 5.