Allen-Bradley MicroLogix 1200 Reference Manual page 167

FRD Instruction Source Operand
The source can be either a word address or the math register. The
maximum BCD source values permissible are:
• 9999 if the source is a word address (allowing only a 4-digit BCD
value)
• 32768 if the source is the math register (allowing a 5-digit BCD value
with the lower 4 digits stored in S:13 and the high order digit in S:14).
If the source is the math register, it must be directly addressed as S:13.
S:13 is the only status file element that can be used.
Updates to Math Status Bits
Table 11.9 Math Status Bits
With this Bit:
S:0/0 Carry
S:0/1 Overflow
S:0/2 Zero Bit
S:0/3 Sign Bit
Always provide ladder logic filtering of all BCD input
NOTE
devices prior to performing the FRD instruction. The
slightest difference in point-to-point input filter delay can
cause the FRD instruction to overflow due to the
conversion of a non-BCD digit.
EQU
S:1
EQUAL
]/[
Source
15
Source
The two rungs shown cause the controller to verify that the value I:0
remains the same for two consecutive scans before it executes the FRD.
This prevents the FRD from converting a non-BCD value during an input
value change.
The Controller:
always resets
sets if non-BCD value is contained at the source or the value to be
converted is greater than 32,767; otherwise resets. On overflow,
the minor error flag is also set.
sets if result is zero, otherwise resets
always resets
A N7:1
0
B I:0.0
0
Conversion Instructions
FRD
FROM BCD
Source I:0.0
0
Dest N7:2
0
MOV
MOVE
Source I:0.0
0
Dest N7:1
0
Publication 1762-RM001C-EN-P
11-5