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Programming Details
Table 2-2. MV64360 Power-Up Configuration Settings (continued)
2
Device
AD Bus
Signal
AD[18]
AD[19]
AD[21:20] Resistors
AD[24:22] Resistors
AD[25]
AD[28:26] Resistors
2-6
Default
Select
Power-Up
Option
Setting
Resistor
1
Resistor
1
01
000
Fixed
0
101
Description
State of Bit vs. Function
DRAM Clock
0
Select
1
DRAM
0
Address/Contr
ol Delay
1
DRAM control
00
path pipeline
01
select
10
11
DRAM read
000
path control
100
001
111
Gigabit port 3
0
Enable
1
PCI_1 DLL
000
control
001
101
110
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DRAM is running at a
higher frequency than the
core clock
DRAM is running at a same
frequency as the core clock
DRAM address and control
signals toggle on falling
edge of DRAM clock
DRAM address and control
signals toggle on rising edge
of DRAM clock
Reserved
Two Pipe stages
Reserved
Three pipe stages
DRAM running in sync
mode
DRAM running in async
mode
Disable
Enable
DLL disable
Conventional PCI mode at
66MHz
PCI-X mode at 133 MHz
PCI-X mode at 66 MHz
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