Pll Circuits - Icom IC-F2610 Service Manual

4-2-2 MODULATION CIRCUIT
The modulation circuit modulates the VCO oscillating signal
(RF signal) using the microphone AF signals.
The AF signals from the level controller (IC5) change the
reactance of varactor diode (D46) to modulate the oscillated
signal at the Tx VCO circuit (Q23). The modulated VCO sig-
nal is amplified at the buffer amplifiers (Q19, Q20) and is
then applied to the drive amplifier circuit via the T/R switch
(D17).
The CTCSS/DTCS signals from the CPU (IC20, pin 44) are
amplified at the buffer amplifier (Q504). The amplified sig-
nals pass through the level controller (IC5, pins 1, 2) and are
then applied to VCO circuit via the low-pass filter (IC21a).
When /NWC signal which is applied to N/W switch (Q64) is
high level, N/W switch (Q64) changes the input level of the
level controller (IC5), thus narrowing the bandwidth.
4-2-3 DRIVE/POWER AMPLIFIER CIRCUITS
The amplifier circuit amplifies the VCO oscillationg signal to
an output power level.
The signal from the buffer amplifier (Q20) passes through
the T/R switch (D17), and is amplified at the drive amplifiers
(Q17–Q15) and power module (IC11) to obtain 25 W of RF
power.
The amplified signal is passed through the antenna switch-
ing circuit (D4), low-pass filter and APC detector. Then the
signal is applied to the antenna connector.
The collector voltages for driver (Q16) come from the MT8V
regulator (Q38, D28). The transmit mute switch (Q39) con-
trols the MT8V regulator when transmit mute is necessary.
• APC CIRCUIT
Tx signal
from Q16
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Q15 IC11
Drive Power
amp. amp.
Q11
VCC
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4-2-4 APC CIRCUIT
The APC circuit protects the power module (IC11) from a
mismatched output load and stabilizes the output power.
The APC detector circuit detects forward signals and reflec-
tion signals at D3 and D1 respectively. The combined volt-
age is at a minimum level when the antenna impedance is
matched at 50 Ω and is increased when it is mismatched.
The detected voltage is applied to the inverse amplifier
(IC10b, pin 5), and the power setting voltage (PSET) is
applied to the other input (IC10b, pin 6) via the amplifier
(IC10a). When antenna impedance is mismatched, the
detected voltage exceeds the power setting voltage. Then
the output voltage of the inverse amplifier (IC10b, pin 7) con-
trols the input current of the power module (IC11) to reduce
the output power via the APC driver (Q11).

4-3 PLL CIRCUITS

4-3-1 PLL CIRCUIT
A PLL circuit provides stable oscillation of the transmit fre-
quency and receive 1st LO frequency. The PLL circuit con-
sists of the PLL IC, charge pump, loop filter and reference
oscillator and employs a pulse swallow counter.
Oscillated signals from the VCO via the buffer amplifiers
(Q19, Q18) are prescaled in the PLL IC (IC12, pin 11) based
on the divided ratio (N-data). The PLL IC detects the out-of-
step phase using the reference frequency and outputs it
from pin 6 (IC12). The output signal is passed through the
charge pump (Q30–Q33) and loop filters (R154/C181,
R153/C179), and is then applied to the VCO circuit as the
lock voltage.
The accelerator switch (IC13) selects the effective loop filter
to accelerate the PLL lock up speed.
FOR
REV
D3
IC10b
5
+
7
6
—
4 - 3
to antenna
connector
D1
PSET
IC10a
3
+
1
2
—