Port Allocations - Icom IC-F2610 Service Manual

4-5 PORT ALLOCATIONS

CPU (IC20)
Pin Port
number name
20 PTTO
21 PTTI
22 AFON
24 BUSY
25 POSW
30 MMUT
31 RMUT
32 NOIS
38 AFV
40 RSSI
43 CDEC
44 CENC
ECS2,
47, 48
ECS1
49 ECK
50 ESI
51 ESO
53 BEEP
55 MCON
56 AMUT
25 NWC
57 HFSW
60 PA
62 TMUT
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Description
Outputs the PTT control signal.
Low : While transmitting
Input port for the PTT control signal
from PTTO port.
Input port for the AF amplifier ON sig-
nal from an optional unit.
Outputs busy signal for an optional
unit.
Input port for the power switch.
Low : While power switch is pushed
Input port for microphone audio mute
control signal from an optional unit.
Input port for receive audio mute con-
trol signal from an optional unit.
Input port for noise signals (pulse-
type) for noise squelch operation.
Input port for the volume control.
Input port for receiving signal strength
level detection.
Input port for CTCSS/DTCS decoding.
Output ports for CTCSS/DTCS sig-
nals.
Output ports for EEPROM select sig-
nals.
ECS1: For internal EEPROM (IC27)
ECS2: For optional EEPROM
Outputs clock signal for EEPROMs.
Input port for serial signal from
EEPROMs.
Outputs serial signal for EEPROMs.
Outputs beep audio signals.
Outputs mic. audio mute control signal
to the audio switch (IC25).
High : While DTMF signals are being
transmitted, etc.
Outputs the AF mute switch (Q6) con-
trol signal.
High : While squelched, etc.
Outputs N/W switch control signals.
High : While wide is selected
Outputs high-pass filter's characteris-
tics select signal.
High : During CTCSS operation
Outputs mic. audio select signal to the
audio switch (IC25).
High : While "Public-address" func-
tion is ON
Outputs MT8V regulator circuit (Q38,
D27) control signal.
High : While transmit is muted.
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Pin Port
number name
Outputs strobe signals for the level
64 DSTB
controller. (IC5)
Outputs data signal for the level con-
65 DDA
troller (IC5).
Outputs clock signal for the level con-
66 DCK
troller (IC5).
Outputs strobe signals for the PLL IC
67 PSTB
(IC12).
Outputs data signal for the PLL IC
68 PDA
(IC12).
Outputs clock signal for the PLL IC
69 PCK
(IC12).
Input port for the PLL unlock signal.
72 UNLK
High : During unlock
Outputs PLL accelerator control signal.
73 PLLT
High : While scanning, etc.
Outputs the T8V regulator circuit (Q38,
75 VTX D28) control signal.
Low : While transmitting
Outputs the R8V regulator circuit
76 VRX (Q36, D27) control signal.
Low : While receiving
Outputs the power control circuit (Q12)
77 PWON control signal.
High : During power ON
Outputs "Public-address" mute signal.
78 PASP High : While PA and Ext. SP func-
Outputs the mute switch (Q7) control
79 SP signal (incl. beep).
High : While squelched, etc.
Input port for an external LCD back-
80 DIM light brightness control signal.
Low : LCD backlight is dimmed
DTR1–
DTR4,
82–89 Outputs DTMF audio signals.
DTC4–
DTC1
Outputs high level control signal for the
pre-set time to the connected external
93 HORN
unit when matched 2- or 5-tone code is
received.
99 SIFT Outputs CPU clock shift signal.
4 - 5
Description
tions are not used