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Hardware Platform
Introduction
In this chapter, the hardware architecture of the Xilinx® Acceleration KCU1500 4DDR
Expanded Partial Configuration platform is described from the perspective of its Vivado
integrator block diagram representation, in six parts, as follows:
•
Host Connectivity
•
Memory Control
•
SDAccel OpenCL Programmable Region IP and the Programmable Region
•
AXI Interconnectivity
•
Application Profiling and Other Features
•
Clocking and Reset
The top level of the platform block diagram in the default IP integrator view shows the static
base region and reconfigurable expanded region as two hierarchical cells, connected by
interfaces and wires. To simplify the view, the Show interface connections only option can
be used.
Figure 3-1
chapter makes use of both views as appropriate.
Kintex UltraScale KCU1500 Acceleration Development Board
UG1234 (v2017.1) June 20, 2017
and
Figure
3-2, show the views respectively. The remainder of this
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Chapter 3
®
IP
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