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Use with the SDAccel Environment
When implemented and used to produce a DSA, the Hardware Platform is suitable for use
with the SDAccel Environment and Software Platform. Generally speaking, this is enabled by
the following characteristics, each of which is described in more detail throughout this
document.
•
The SDAccel OpenCL Programmable Region IP core: This IP core in the
reconfigurable expanded region of the platform provides the SDAccel System Compiler
with both a logical hierarchy and a large physical area (herein together referred to as
the Programmable Region) to replace with the compiled user kernel and required
interconnect, using partial reconfiguration. The physical area available to the
Programmable Region with user kernels is the expanded region, as described above.
•
Software compatibility: The memory-mapped IP cores, including the SDAccel OpenCL
Programmable Region IP core, are configured to use address offsets and ranges that
are compatible with the hardware abstraction Layer (HAL) driver provided with the
SDx™ Environments installation. The kernel mode drivers for the Xilinx DMA subsystem
for PCI Express are likewise provided with the SDx Environments installation.
•
Global memory access: DDR4 SDRAM global memory is accessible to both the host
and user kernels using AXI4 memory-mapped connectivity provided by AXI
SmartConnect IP. Memory access capabilities are described in
Connectivity.
•
DSA metadata: The necessary Vivado project properties are applied such that the DSA
creation phase captures the metadata for use with the SDAccel System Compiler.
For detailed guidance on the DSA creation process, see the SDAccel Environment Platform
Development Guide (UG1164)
Kintex UltraScale KCU1500 Acceleration Development Board
UG1234 (v2017.1) June 20, 2017
[Ref
2].
www.xilinx.com
Chapter 2: Platform Characteristics
Sparse Memory
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