Chapter 2: Platform Characteristics; Introduction; Expanded Partial Reconfiguration - Xilinx Kintex UltraScale KCU1500 User Manual

Sdaccel platform acceleration development board
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Platform Characteristics

Introduction

The Xilinx® Acceleration KCU1500 4DDR Expanded Partial Reconfiguration platform is a
high-performance acceleration platform for the SDAccel™ Environment. The following
sections describe its distinguishing characteristics.

Expanded Partial Reconfiguration

Many device support archives (DSAs) use partial reconfiguration to enable compiled binary
downloads to the accelerator device while it remains online and linked to the PCIe® bus of
the host. The Xilinx Acceleration KCU1500 4DDR Expanded Partial Reconfiguration platform
is also designed for partial reconfiguration, but provides a larger, "expanded region" that
makes over 80% of the overall fabric resources on the KU115 device available to the kernels.
Only he logic necessary for keeping the link active and device operational, primarily the
Xilinx DMA subsystem for PCI Express, basic control interfaces, and clock sources, is
contained within a static "base region" floorplanned to less than 8% of the device area that
cannot be used for kernel resources.
To make these additional fabric resources available to implemented kernel logic, the data
path SmartConnect IPs, trace offload hardware infrastructure, SDAccel OpenCL
Programmable Region IP, and all four of the DDR4 memory controller IPs are contained
within the partially reconfigurable "expanded region" level of hierarchy. When the SDAccel
System Compiler executes, kernel logic is placed and routed among these necessary
resources, and a partial bitstream containing them is produced and included in the
compiled binary.
An outcome of locating the DDR4 memory controllers in the reconfigurable region is that
IMPORTANT:
DDR4 global memory content is lost when a new partial bitstream is downloaded.
Figure 2-1
shows the IP integrator block diagram view of the top-level of the platform,
colored to show the static base logical hierarchy in yellow, and the reconfigurable expanded
region in green.
Kintex UltraScale KCU1500 Acceleration Development Board
UG1234 (v2017.1) June 20, 2017
www.xilinx.com
Chapter 2
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