Introduction; Address Map - Xilinx Kintex UltraScale KCU1500 User Manual

Software Platform

Introduction

The Xilinx® Acceleration KCU1500 4DDR Expanded Partial Configuration platform is a
memory-mapped system with PCIe® host connectivity supported by a kernel mode DMA
driver for the XDMA IP. A hardware abstraction layer (HAL) driver isolates the SDAccel™
Software Platform runtime software from the implementation details of the kernel mode
drivers, which interact with the platform hardware based on a known address mapping.
This chapter provides the address map and the software layers for the design.

Address Map

The IP integrator block diagram specifies the following address map for the IP cores in the
reference design. The xlcdma driver defines these offsets in its header files.
Table 4-1: Reference Design Address Map
Master IP Core AXI Master Interface
XDMA, through S_AXI_MGNTPF
dma_pf_demux AXI4-Lite control
interface for
Management
Physical Function
Kintex UltraScale KCU1500 Acceleration Development Board
UG1234 (v2017.1) June 20, 2017
AXI Slave
Slave IP Core
Interface
S_AXI
u_ocl_region
SDAccel
OpenCL
Programmable
Region
S_AXI_LITE
axi_hwicap
AXI HWICAP for
partial
bitstream
download
S_AXI
gate_pr
GPIO for partial
reconfiguration
isolation
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Chapter 4
Offset
Range High Address
Address
0x0000_0000 128K 0x0001_FFFF
0x0002_0000 64K 0x0002_FFFF
0x0003_0000 4K 0x0003_0FFF
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