Xilinx Kintex UltraScale KCU1500 User Manual page 9

X-Ref Target - Figure 2-1
Figure 2-1: IP Integrator Top-Level View of Platform, Showing Base and Expanded Regions
Correspondingly,
where utilized and floorplanned static base region logic is highlighted yellow, and utilized
expanded region logic is highlighted green.
In addition to the prominent rectangular regions of DDR4 memory controller IP instances,
the reconfigurable expanded region contains the placeholder "add one" kernel, which is
replaced by the implemented user kernel in the SDAccel System Compiler flow.
X-Ref Target - Figure 2-2
Figure 2-2: Device View of Implemented Platform, Showing Base and Expanded Regions
Kintex UltraScale KCU1500 Acceleration Development Board
UG1234 (v2017.1) June 20, 2017
Figure 2-2 shows the Vivado
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Chapter 2: Platform Characteristics
®
device view of the implemented platform,
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