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Stacked Silicon Interconnect (SSI) Technology
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The Kintex
UltraScale™ KU115 device uses SSI technology and contains two super logic
regions (SLRs). Though the high availability of total fabric resources is clearly beneficial, the
delay penalty for routes that cross from one SLR to another can be significant, and make
timing closure challenging in highly connected designs such as the Xilinx Acceleration
KCU1500 4DDR Expanded Partial Reconfiguration platform. The AXI data paths used
throughout the platform are wide and generally include combinatorial paths to implement
the AXI4 memory-mapped protocol, making it imperative that such paths which cross into
the other SLR are well-controlled and contain as few logic levels as possible. The platform
uses optimized IP configurations, careful partitioning, and floorplanning where necessary
to achieve this control and improve routability and timing closure.
The static base region of the design is floorplanned to the bottom-right corner of the lower
SLR, corresponding to the location of the utilized PCI Express 3.x Integrated Block. Two of
the four DDR4 SDRAM memory controller IP instances are floorplanned to the lower SLR, in
regions around the High Performance I/O banks they utilize. The remaining two DDR4
SDRAM memory controller IP instances are floorplanned to the upper SLR, in regions
around the High Performance I/O banks they utilize.
The required physical locations suggest the following design partitioning that is used in the
platform:
•
The Xilinx DMA subsystem for PCIe instance is floorplanned to the static base region of
the lower SLR.
•
The AXI SmartConnect 1x5 (1 slave interface, 5 master interfaces) instance which
connects the Xilinx DMA subsystem for PCIe IP to the four AXI SmartConnect 2x1
instances and the AXI Performance Monitor is floorplanned to the reconfigurable
expanded region of the lower SLR.
•
The two AXI SmartConnect 2x1 instances which each connect the Programmable
Region and host to a DDR4 SDRAM memory controller IP instance in the lower SLR are
floorplanned to the lower SLR, except:
Input pipeline stages on the master interfaces connected to the Programmable
°
Region are not floorplanned, facilitating potential SLR crossing through automatic
placement when user kernels are automatically placed in the upper SLR.
•
The two AXI SmartConnect 2x1 instances which each connect the Programmable
Region and host to a DDR4 SDRAM memory controller IP instance in the upper SLR are
floorplanned to the upper SLR, except:
Input pipeline stages on the master interfaces connected to the Programmable
°
Region are not floorplanned, facilitating potential SLR crossing through automatic
placement when user kernels are automatically placed in the lower SLR.
Kintex UltraScale KCU1500 Acceleration Development Board
UG1234 (v2017.1) June 20, 2017
www.xilinx.com
Chapter 2: Platform Characteristics
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