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IDT EB8T5A Eval Board Manual

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IDT
89EBPES8T5A
™
Evaluation Board Manual
(Eval Board: 18-636-002)
July 2009
6024 Silver Creek Valley Road, San Jose, California 95138
Telephone: (800) 345-7015 • (408) 284-8200 • FAX: (408) 284-2775
Printed in U.S.A.
©2009 Integrated Device Technology, Inc.

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  • Page 1 ® 89EBPES8T5A ™ Evaluation Board Manual (Eval Board: 18-636-002) July 2009 6024 Silver Creek Valley Road, San Jose, California 95138 Telephone: (800) 345-7015 • (408) 284-8200 • FAX: (408) 284-2775 Printed in U.S.A. ©2009 Integrated Device Technology, Inc.
  • Page 2 Integrated Device Technology, Inc. reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply the best possible product. IDT does not assume any responsibility for use of any circuitry described other than the circuitry embodied in an IDT product. The Company makes no representations that circuitry described herein is free from patent infringement or other rights of third parties which may result from its use.

  • Page 3: Table Of Contents

    Table of Contents ® Description of the EB8T5A Eval Board Notes Introduction ............................. 1-1 Board Features ..........................1-2 Hardware ..........................1-2 Software..........................1-2 Other............................1-2 Revision History ..........................1-3 Installation of the EB8T5A Eval Board EB8T5A Installation ........................2-1 Hardware Description ........................2-1 Host System ...........................
  • Page 4 IDT Table of Contents Notes EB8T5A Eval Board Manual July 23, 2009...
  • Page 5 Attention Buttons ......................2-11 Table 2.15 Miscellaneous Jumpers, Headers ..................2-11 Table 2.16 LED Indicators ........................2-13 Table 2.17 PCI Express x4 Connector Pinout ..................2-14 Table 2.18 PCI Express x1 Connector Pinout ..................2-15 EB8T5A Eval Board Manual July 23, 2009...
  • Page 6 IDT List of Tables Notes EB8T5A Eval Board Manual July 23, 2009...
  • Page 7 List of Figures ® Figure 1.1 Function Block Diagram of the EB8T5A Eval Board ............1-1 Notes Figure 2.1 Clock Distribution Block Diagram ..................2-3 Figure 2.2 Power Distribution Block Diagram ..................2-4 Figure 2.3 APWRDIS# Timing ......................2-5 Figure 2.4 APWRDIS# Timing Circuit ....................2-5...
  • Page 8 IDT List of Figures Notes EB8T5A Eval Board Manual July 23, 2009...

  • Page 9: Introduction

    PES8T5A switch. It is also a cost effective way to add a PCIe downstream port (x1) to an existing system with a limited number of PCIe downstream ports. The EB8T5A eval board is designed to function as an add-on card to be plugged into a x4 PCIe slot available on a motherboard hosting an appro- priate root complex, microprocessor(s), and four downstream ports.

  • Page 10: Board Features

    IDT Description of the EB8T5A Eval Board Board Features Notes Hardware PCIe 5 port switch – PES8T5A — Five ports (one x4 port and four x1 ports), 8 PCIe lanes – PES6T5 — Five ports (one x2 port and four x1 ports), 6 PCIe lanes –...

  • Page 11: Revision History

    IDT Description of the EB8T5A Eval Board Revision History Notes September 10, 2007: Initial publication of board manual. July 23, 2009: Added PES6T5 and PES5T5 devices to eval board manual. Updated Power Sources section, Table 2.15, and Schematics. Added Note after Table 2.17.
  • Page 12 IDT Description of the EB8T5A Eval Board Notes EB8T5A Eval Board Manual 1 - 4 July 23, 2009...

  • Page 13: Installation Of The Eb8T5A Eval Board

    Clock Configuration Switch - S3[3] S3[3] Clock Source Onboard Reference Clock – Use onboard clock generator Upstream Reference Clock – Host system provides clock (Default) Table 2.1 Clock Source Selection EB8T5A Eval Board Manual 2 - 1 July 23, 2009...

  • Page 14: Clock Frequency Selection

    IDT Installation of the EB8T5A Eval Board Notes The source for the onboard clock is the ICS9FG104 clock generator device (U8) connected to a 25MHz oscillator (Y1). When using the onboard clock generator, the EB8T5A allows selection between multiple clock rates and spread spectrum settings via DIP switches as described in Tables 2.2 and 2.3 respectively.

  • Page 15: Power Sources

    IDT Installation of the EB8T5A Eval Board Notes PEREFCLK0 Upstream PEREFCLK Port2 SMA - J18,J19 ICS557-06 Port3 ICS9DB803D Port4 25MHz ISC9FG104 Port5 Figure 2.1 Clock Distribution Block Diagram Power Sources Power for the EB8T5A is generated from the 12.0V PCI Express upstream slot power or optionally from 3.3Vaux.

  • Page 16: Vaux Support

    IDT Installation of the EB8T5A Eval Board Notes Figure 2.2 Power Distribution Block Diagram Vaux Support Power supply support will be provided to EB8T5A from 12.0V upstream power to 3.3Vaux upstream power when in sleep mode. The WAKE# signal direction, both an input and output will be supported by jumper selection.
  • Page 17 IDT Installation of the EB8T5A Eval Board Notes Figure 2.3 APWRDIS# Timing On initial power up APWRDIS# must be held low initially for 8 clocks after PERST# is removed. Then it must be sampled high 256 clocks after PERSTN# is removed to enable L2 mode. Subsequent PERST# will not affect the APWRDIS# state.

  • Page 18: Pci Express Serial Data Transmit Termination Voltage Converter

    IDT Installation of the EB8T5A Eval Board PCI Express Serial Data Transmit Termination Voltage Converter Notes A DC-DC converter (U6) provides a 1.5V PCI Express serial data transmit termination voltage (shown as VTTPE or VPETVTT) to the PES8T5A. PCI Express Digital Power Voltage Converter A separate DC-DC converter (U16) provides a 1.0V PCI Express digital power voltage (VDDPE) to the...

  • Page 19: Downstream Reset

    IDT Installation of the EB8T5A Eval Board Notes • The host system board IO Controller Hub asserting PERST# signal, which propagates through the PCIe upstream edge connector of the EB8T5A. Note that one can bypass the onboard voltage monitor (TLC7733D) by moving the shunt from pin 1-2 to pin 2-3 (default) on W2.

  • Page 20: Smbus Interfaces

    IDT Installation of the EB8T5A Eval Board Notes Signal Description SWMODE[2:0] Switch Mode. These configuration pins determine the PES8T5A switch operating mode. Default: 0x0 0x0 - Normal switch mode 0x1 - Normal switch mode with Serial EEPROM-based initialization 0x2 through 0x8 - Reserved REFCLKM PCI Express Reference Clock Mode Select.

  • Page 21: Table 2.9 Slave Smbus Interface Connector

    IDT Installation of the EB8T5A Eval Board Notes Slave SMBus Interface Connector Signal Table 2.9 Slave SMBus Interface Connector A fixed slave SMBus address specified by the SSMBADDR[5,3:1] pins is used. For a fixed address, the SMBus address of the PES8T5A slave interface is 0b1110111 by default and is configurable using DIP switch S4 as described in Tables 2.10 and 2.11.

  • Page 22: Smbus Master Interface

    IDT Installation of the EB8T5A Eval Board Notes SMBUS Slave Interface Address Setting S4[4] S4[3] S4[2] S4[1] Slave Interface SSMBADDR[5] SSMBADDR[3] SSMBADDR[2] SSMBADDR[1] Bus Address 0b1100101 0b1100100 0b1100011 0b1100010 0b1100001 0b1100000 Table 2.11 PES8T5A SMBus Slave Interface Address Setting (Part 2 of 2) The slave SMBus interface responds to the following SMBus transactions initiated by an SMBus master.

  • Page 23: Attention Buttons

    IDT Installation of the EB8T5A Eval Board Notes JTAG Connector J2 Signal Direction Signal Direction /TRST - Test reset Input — TDI - Test data Input — TDO - Test data Output — TMS - Test mode select Input —...

  • Page 24: Leds

    IDT Installation of the EB8T5A Eval Board Notes Miscellaneous Jumpers, Headers Ref. Type Default Description Designator Header 2-3 Shunted 1-2: Port 2, +3.3V source base on hot-plug controller 2-3: Port 2, +3.3V source from upstream port power Header 2-3 Shunted...

  • Page 25: Table 2.16 Led Indicators

    IDT Installation of the EB8T5A Eval Board Notes Location Color Definition DS87 Green Port 2: Power-is-good indicator DS86 Green Port 3: Power-is-good indicator DS85 Green Port 4: Power-is-good indicator DS84 Green Port 5: Power-is-good indicator DS83 Amber Port2: Attention Input indicator...

  • Page 26: Pci Express Connectors

    IDT Installation of the EB8T5A Eval Board Notes Location Color Definition DS103 Amber Port3: Link Activity indicator DS102 Amber Port4: Link Activity indicator DS101 Amber Port5: Link Activity indicator Table 2.16 LED Indicators (Part 2 of 2) PCI Express Connectors...

  • Page 27: Table 2.18 Pci Express X1 Connector Pinout

    IDT Installation of the EB8T5A Eval Board Notes Side A Side B PETp3 Transmitter differential Ground PETn3 pair, Lane 3 Ground Ground PERp3 Receiver differential RSVD Reserved PERn3 pair, Lane 3 PRSNT2# Hot-Plug presence detect Ground Ground RSVD Reserved Table 2.17 PCI Express x4 Connector Pinout (Part 2 of 2) Note: R347 should be populated with a 0 ohm resistor (0402) for systems that require PRSNT2# for the x1 width to be connected.

  • Page 28: Eb8T5A Board Figure

    IDT Installation of the EB8T5A Eval Board EB8T5A Board Figure EB8T5A Eval Board Manual 2 - 16 July 23, 2009...

  • Page 29: Software For The Eb8T5A Eval Board

    PCIe parts from IDT. Once users are familiar with the GUI, they will be able to use the same GUI on all PCIe parts from IDT. This software is customized for each device through an XML device description file which includes information on the number of ports, registers, types of registers, information on bit-fields within each register, etc.
  • Page 30 IDT Software for the EB8T5A Eval Board Notes EB8T5A Eval Board Manual 3 - 2 July 23, 2009...

  • Page 31: Schematics

    Chapter 4 Schematics ® Schematics Notes EB8T5A Eval Board Manual 4 - 1 July 23, 2009...
  • Page 32 FAB P/N REV. SCH-00162 18-636-002 AUTHOR CHECKED BY CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC. T. Tran D. Huang 6024 SILVER CREEK VALLEY RD. SAN JOSE, CA 95138 COPYRIGHT (C) IDT 2008 Tue Apr 15 14:25:57 2008 SHEET 1 OF 17...
  • Page 33 FAB P/N REV. SCH-00162 18-636-002 AUTHOR CHECKED BY CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC. T. Tran D. Huang 6024 SILVER CREEK VALLEY RD. SAN JOSE, CA 95138 COPYRIGHT (C) IDT 2008 Thu Apr 24 10:22:10 2008 SHEET 2 OF 17...

  • Page 34: Power Mosfets For 3.3Vaux

    FAB P/N REV. SCH-00162 18-636-002 AUTHOR CHECKED BY CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC. T. Tran D. Huang 6024 SILVER CREEK VALLEY RD. SAN JOSE, CA 95138 COPYRIGHT (C) IDT 2008 Thu Apr 24 10:22:11 2008 SHEET 3 OF 17...

  • Page 35: Clocks

    FAB P/N REV. SCH-00162 18-636-002 AUTHOR CHECKED BY CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC. T. Tran D. Huang 6024 SILVER CREEK VALLEY RD. SAN JOSE, CA 95138 COPYRIGHT (C) IDT 2008 Thu Apr 24 10:22:12 2008 SHEET 4 OF 17...

  • Page 36: Reset,Smbus,Jtag,Dipsw

    FAB P/N REV. SCH-00162 18-636-002 AUTHOR CHECKED BY CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC. T. Tran D. Huang 6024 SILVER CREEK VALLEY RD. SAN JOSE, CA 95138 COPYRIGHT (C) IDT 2008 Thu Apr 24 10:22:13 2008 SHEET 5 OF 17...

  • Page 37: Apwrdisn Timing Circuit

    FAB P/N REV. SCH-00162 18-636-002 AUTHOR CHECKED BY CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC. T. Tran D. Huang 6024 SILVER CREEK VALLEY RD. SAN JOSE, CA 95138 COPYRIGHT (C) IDT 2008 Thu Apr 24 10:22:13 2008 SHEET 6 OF 17...
  • Page 38 FAB P/N REV. SCH-00162 18-636-002 AUTHOR CHECKED BY CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC. T. Tran D. Huang 6024 SILVER CREEK VALLEY RD. SAN JOSE, CA 95138 COPYRIGHT (C) IDT 2008 Thu Apr 24 10:22:14 2008 SHEET 7 OF 17...

  • Page 39: Io Expanders

    FAB P/N REV. SCH-00162 18-636-002 AUTHOR CHECKED BY CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC. T. Tran D. Huang 6024 SILVER CREEK VALLEY RD. SAN JOSE, CA 95138 COPYRIGHT (C) IDT 2008 Thu Apr 24 10:22:14 2008 SHEET 8 OF 17...

  • Page 40: Io Expander Leds

    FAB P/N REV. SCH-00162 18-636-002 AUTHOR CHECKED BY CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC. T. Tran D. Huang 6024 SILVER CREEK VALLEY RD. SAN JOSE, CA 95138 COPYRIGHT (C) IDT 2008 Thu Apr 24 10:22:15 2008 SHEET 9 OF 17...

  • Page 41: Hot Swap Control Port 2/3

    FAB P/N REV. SCH-00162 18-636-002 AUTHOR CHECKED BY CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC. T. Tran D. Huang 6024 SILVER CREEK VALLEY RD. SAN JOSE, CA 95138 COPYRIGHT (C) IDT 2008 Thu Apr 24 10:22:16 2008 SHEET 10 OF 17...

  • Page 42: Hot Swap Control Port 3/5

    FAB P/N REV. SCH-00162 18-636-002 AUTHOR CHECKED BY CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC. T. Tran D. Huang 6024 SILVER CREEK VALLEY RD. SAN JOSE, CA 95138 COPYRIGHT (C) IDT 2008 Thu Apr 24 10:22:16 2008 SHEET 11 OF 17...

  • Page 43: Pes8T5A - Clock,Smbus,Gpio

    FAB P/N REV. SCH-00162 18-636-002 AUTHOR CHECKED BY CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC. T. Tran D. Huang 6024 SILVER CREEK VALLEY RD. SAN JOSE, CA 95138 COPYRIGHT (C) IDT 2008 Thu Apr 24 10:22:17 2008 SHEET 12 OF 17...

  • Page 44: Pes8T5A - Port

    FAB P/N REV. SCH-00162 18-636-002 AUTHOR CHECKED BY CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC. T. Tran D. Huang 6024 SILVER CREEK VALLEY RD. SAN JOSE, CA 95138 COPYRIGHT (C) IDT 2008 Thu Apr 24 10:22:17 2008 SHEET 13 OF 17...

  • Page 45: Pes8T5A Downstream Ports

    FAB P/N REV. SCH-00162 18-636-002 AUTHOR CHECKED BY CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC. T. Tran D. Huang 6024 SILVER CREEK VALLEY RD. SAN JOSE, CA 95138 COPYRIGHT (C) IDT 2008 Thu Apr 24 10:22:18 2008 SHEET 14 OF 17...
  • Page 46 FAB P/N REV. SCH-00162 18-636-002 AUTHOR CHECKED BY CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC. T. Tran D. Huang 6024 SILVER CREEK VALLEY RD. SAN JOSE, CA 95138 COPYRIGHT (C) IDT 2008 Thu Apr 24 10:22:18 2008 SHEET 15 OF 17...
  • Page 47 FAB P/N REV. SCH-00162 18-636-002 AUTHOR CHECKED BY CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC. T. Tran D. Huang 6024 SILVER CREEK VALLEY RD. SAN JOSE, CA 95138 COPYRIGHT (C) IDT 2008 Thu Apr 24 10:22:19 2008 SHEET 16 OF 17...

  • Page 48: Pes8T5A Power

    FAB P/N REV. SCH-00162 18-636-002 AUTHOR CHECKED BY CONFIDENTIAL PROPERTY OF INTEGRATED DEVICE TECHNOLOGY, INC. T. Tran D. Huang 6024 SILVER CREEK VALLEY RD. SAN JOSE, CA 95138 COPYRIGHT (C) IDT 2008 Thu Apr 24 10:22:19 2008 SHEET 17 OF 17...

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