Configuring Internal Vreg Mode - NXP Semiconductors S32R274 EVB User Manual

4.13 Configuring Internal VREG Mode

Table 13 shows the jumper configuration for the EVB when in internal VREG mode.
Jumper Number
J2
J3
J5
J7
J8
J9
J10
J11
J21
J30
J31
J32
J33
J34
J35
J36
J39
J40
J43
J44
J45
J46
J47
J48
J13
J17
J24
J16
J18
J37
J42
Table 13. Jumper Configuration for Internal VREG mode
Default position
3-4
3-4
3-4
3-4
on
on
1-2
1-2, 3-4
2-3
on
1-2, 3-4
on
on
on
on
on
on
on
off
off
on
on
on
on
Headers
off
off
off
off
off
off
off
1.25v supply
5.0v supply to create 3.3v for the AFE Regulator
3.3v supply for the device
5.0v Linear supply from Motherboard for SAR ADC
Reference voltage
1.25v MIPI-CSI2 DPHY
3.3v IO
Determine internal or external Vreg Mode
ACD Ref
VPP TEST (always GND)
3.3v RGMII
Linflex Tx/Rx
Jumper to supply to transistor
Jumper supplies 1.25v to the core
3.3v supply to PMU
1.25v PLL supply
3.3v Flash supply
3.3v ADC supply
3.3v supply to MCU
CAN2 Tx connection to PHY
CAN2 Rx connection to PHY
Flexray TXD A connection to motherboard
Flexray TXEN A connection to motherboard
RESET_B Connection to reset circuit
VREG_POR_B Connection to reset circuit
CTE output
SIPI Interface
JTAG Interface
SD ADC output
DAC output
CAN0 connections
CAN2 connections
S32R274 EVB User Guide
Function
27