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Summary of Contents for NXP Semiconductors SJA1124EVB
- Page 1 Quick Start Guide Part Number Here SJA1124EVB Evaluation Board for SJA1124 SPI to Quad-LIN Bridge Arduino UNO footprint-compatible LIN Communication Shield...
- Page 2 GET TO KNOW THE SJA1124 EVALUATION BOARD J2 Header J1 Header INHN Indicator LEDs VIO Supply Indicator LED 16 x LIN Master 4 x SJA1124 External Power Supply (5-16V) Power Supply J3 Header J4 Header Indicator LED Figure 1: Front side of SJA1124EVB...
- Page 3 Synchronous LIN frame transmission Status SPI Chip Interrupt Selects Figure 2: SJA1124EVB footprint SJA1124EVB Arduino UNO footpint-compatible shield The SJA1124 EVB has the standard-based form factor compatible with Arduino UNO pin layout, that enables rapid prototyping with a wide range of microcontroller development boards.
- Page 4 Quick Start Guide STEP-BY-STEP FEATURES INSTRUCTIONS • 4 x SJA1124A This section describes how to use the SJA1124 evaluation board as a hardware • SPI to LIN bridge plug-in board (shield) that supports up to • Supports 16 x LIN master 16 LIN master connections when plugged channel connectors on existing microcontroller development...
- Page 5 SJA1124 a VIO must be provided. Default reference voltage pin. Default SJA1124EVB setting for CLK pin SJA1124EVB setting for VIO pin mapping is J2-2 (CLK1_SJA). mapping is J3-3 (VDD). As alternative J2-1 (CLK2_SJA) or...
- Page 6 Quick Start Guide J1 HEADER – DEFAULT SETTING Default J1 Header Resistor Setting Signal Description J1-1 Not connected J1-2 Not connected J1-3 INTN_SJA Shared SJA1124 interrupt output J1-4 STAT_SJA Shared SJA1124 SPI status output J1-5 open CLK3_SJA Alternative SJA1124 clock reference J1-6 Not connected J1-7...
- Page 7 www.nxp.com J2 HEADER – DEFAULT SETTING Default J2 Header Resistor Setting Signal Description J2-1 open CLK2_SJA Alternative SJA1124 clock reference J2-2 CLK1_SJA SJA1124 clock reference J2-3 Not connected J2-4 SDI_SJA Shared SJA1124 SPI slave data input J2-5 SDO_SJA Shared SJA1124 SPI slave data output J2-6 SCK_SJA Shared SJA1124 SPI slave clock input...
- Page 8 Quick Start Guide J3 HEADER – DEFAULT SETTING Default J3 Header Resistor Setting Signal Description J3-1 VBAT Power supply J3-2 SJA1124 VIO reference voltage J3-3 Not connected J3-4 open P3V3 Alternative SJA1124 VIO reference voltage J3-5 open P5V0 Alternative SJA1124 VIO reference voltage J3-6 Ground J3-7...
- Page 9 www.nxp.com J4 HEADER – DEFAULT SETTING Default J4 Header Resistor Setting Signal Description J4-1 TMF_SJA Shared SJA1124 transmit frame input J4-2 Not connected J4-3 SCSN_SJA2 SJA1124 SPI chip select input #2 J4-4 SCSN_SJA3 SJA1124 SPI chip select input #3 J4-5 Not connected J4-6 Not connected...
- Page 10 Quick Start Guide J1 PWR HEADER – POWER SUPPLY J1 PWR Header Signal Description J1PWR-1 VBAT Power supply J1PWR-2 Ground J1PWR-3 Ground Figure 8: Power supply circuit...
- Page 11 www.nxp.com J5 – J20 HEADER – LIN BUS Jx Header Default (J5 – J20) Resistor Setting Signal Description Jx-1 LINx LIN bus Jx-2 VBAT Power supply Jx-3 Not connected Jx-4 Ground Figure 8: LIN circuit at SJA1124...
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Page 12: Get Started
SUPPORT Get Started Visit www.nxp.com/support for technical communities and support requests. Download example software and documentation from NXP WARRANTY DocStore (NDA required) Visit www.nxp.com/warranty for complete www.docstore.nxp.com warranty information. In-Vehicle Networking LIN SJA1124 www.nxp.com NXP and the NXP logo are trademarks of NXP B.V. All other product or service names are the property of their respective owners.
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